Hi,
Iam interfacing EMIF16 6678 with IDT7024 4K*16 DPRAM (ASRAM).
As per 6678 recommendation for 16 BIT interface i need to connect A23 of DSP6678 to A0 of DPRAM , A1 to A11 of 6678 to A1 to A11 of DPRAM.
should i connect or i need to change ?.
Also iam using level shifter sn74lvch16t245 in between DSP & DPRAM for 1.8V to 5V level translation.
Propagation delay for latch(40ns) & and gate(used for enabling data bus level shifter) is arround 45ns(worst case). Can i interface 6678 with 25ns DPRAM ?
or i need to connect to 35 or 55ns DPRAM ?.
Iam operating DSP at 1Ghz core clock.---> EMIF 16 clock is 1000Mhz/6--->166.6Mhz.
Maximum timings for read/ write possible with DSP
DSP setup time read/write MAX - 96ns
DSP strobe time read/write MAX - 378 ns(During this time OE low at end of strobe OE is high, DPRAM will sends data when OE is high/ During this time WE low at end of strobe WE is high, DPRAM will samples the data when strobe is high)
DSP hold time read/write MAX - 48 ns
Can i get DPRAM access with Set up time-50ns, Strobe time- 70ns Hold time -30ns.?
Please let me know which is the best solution also let me know if my calculations are wrong?
Note: DSP data lines to level shifter direction will be controlled by OE of DSP & CE1 & CE2 are used for DPRAM memory & Semaphore memory enables.CE1 & CE2 are also connected to AND gate to enable data bus of level shifter.Since data bus is also shared with NAND flash.
---> Data bus will be enabled when CE1 or CE2 are enabled
Thanks & regards,
Prasad.