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C6678 -EMIF 16 bit DPRAM interface

srinivasaprasad saladi
Intellectual 295 points
Other Parts Discussed in Thread: SN74LVCH16T245

Hi,

Iam interfacing EMIF16 6678 with IDT7024 4K*16 DPRAM (ASRAM).
As per 6678 recommendation for 16 BIT interface i need to connect A23 of DSP6678 to A0 of DPRAM , A1 to A11 of 6678 to A1 to A11 of DPRAM.
should i connect  or i need to change ?.
Also iam using level shifter sn74lvch16t245 in between DSP & DPRAM  for 1.8V to 5V level translation.
Propagation delay for latch(40ns) & and gate(used for enabling data bus level shifter) is arround 45ns(worst case). Can i interface 6678 with 25ns DPRAM ?
or i need to connect to 35 or 55ns DPRAM ?.

Iam operating DSP at 1Ghz core clock.---> EMIF 16 clock is 1000Mhz/6--->166.6Mhz.

Maximum timings for read/ write possible with DSP

DSP setup time read/write MAX - 96ns

DSP strobe time read/write  MAX - 378 ns(During this time OE low at end of strobe OE is high, DPRAM will sends data when OE is high/ During this time WE low at end of strobe WE is high, DPRAM will samples the data when strobe is high)

DSP hold time read/write  MAX - 48 ns

Can i get DPRAM access with Set up time-50ns, Strobe time- 70ns Hold time -30ns.?

Please let me know which is the best solution also let me know if my calculations are wrong?

Note: DSP data lines to level shifter direction will be controlled by OE of DSP & CE1 & CE2 are used for DPRAM memory & Semaphore memory enables.CE1 & CE2 are also connected to AND gate to  enable data bus of level shifter.Since data bus is also shared with NAND flash.

---> Data bus will be enabled when CE1 or CE2 are enabled



Thanks & regards,
Prasad.

  • 0
    TI__Mastermind 42545 points

    Hi Prasad,

    I post this in response to the question you posted in the other thread but let me repeat the answer here.

    The connection should be close to the one shown in Figure 2-2 of the Keystone EMIF users guide.  The addressing will be as follows for the IDT 7024.

    Keystone                    IDT7024

    EMIFA23      ->          A0

    EMIFA00      ->          A1

    EMIFA01      ->          A2

        ……………………

    EMIFA09      ->       A10

    EMIFA10      ->       A11

     

    You will need two of the level translators, one for the data and one for the address and command signals.  Using the CE to control the OE on the buffer should work but you’ll have to do a timing analysis to determine what the wait times needed.  The buffer has pretty wide windows so that will require that you add to the length of your bus cycles to ensure the data is present for the time needed.  Don’t forget that this is a dual port memory so you might have to connect the busy signals to the EMIFWAIT to extend a cycle if the memory is being accessed from the other side.

    I haven't finished reviewing the setup numbers you posted above.  I'll post again once I've had a chance to check them.  How are you handling the busy signal?  The busy from the dual port memory isn't open collector so you'll have to include a voltage translator for that signal as well.  You'll have to ensure that it will meet the timing requirements for the EMIFWAIT input to allow it to extend your memory access.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Intellectual 295 points

    Hi Bill,

    Busy signal is indication for illegal access of memory ex:Both ports are writing into same memory.This signal am connecting to DSPGPIO as input indication.

    In DPRAM there is no provision for Wait pin. DSP EMIFWAIT pin i cannot interface with DPRAM.

    Can i manage DPRAM as mentioned in timings, let me know anything needs to change?

    Thanks & Regards,

    Prasad.

  • 0 in reply to srinivasaprasad saladi
    TI__Mastermind 42545 points

    Hi Prasad,

    Hooking the Busy signal to a GPIO is not an acceptable solution.  You won't be able to distinguish which access was bad because there isn't any correlation between the GPIO and the EMIF access.  You must connect the Busy signal to the wait signal and use it to delay an access if a collision occurs.  The wait signal can be programmed to use the polarity of the busy signal but you'll have to do the timing analysis to be sure that it arrives at the DSP at the proper time.  Is there a reason that you've picked a DPRAM that uses 3.3V IO?  If you chose a device that has 3.3V IOs you could use a fast bus switch and a majority of your timing problems would be eliminated.

    Regards, Bill