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USBO endpoint blues

Kurt Jensen
Genius 5040 points

Our device has two IN endpoints and one OUT endpoint. EP1 is used for control and status on the device.  I am working on sending batches of data to the PC via EP2. After sending bytes over EP2 I can no longer send anything over EP1.

Here is a relative sequence:

EP1 - read control, write status, two way communication via EP1
...
EP1 - read command to send batch of data
EP2 - write batch of data
EP1 - read request for status
EP1 - write status

The PC is not receiving the status and repeatedly sends requests. Each time I get a request I write to EP1 but nothing gets through.  None of the USB0 register bits seems out of order (that I can tell since there are a LOT of them...)  I've looked at the FIFOs, control and status for endpoint 1, control and status for endpoint 2, etc. EP1 communication works fine until send data over EP2. Then I can receive over EP1 but not send.

Andy ideas?  Questions?

  • 0
    Intellectual 500 points

    Kurt,

    Your message does not contain enough information to usefully help you. I would suggest that if you are using the index register that you are not setting it correctly between configuring each EP, and that is why after sending data via EP2 your EP1 transport fails...but as I said there isn't enough info for me to truely help you.

    As an aside, the company I work for has a licenseable fully working usb driver that enables the C6000 device to appear as up to three serial ports, so would suit your application of two ports, one sending and receiving and the other just sending from the DSP. If you are interested, then please email me. We may also be able to assist you with your actual needs, but we have been through the pain of getting the USB to work effectively, and I believe our driver offers significant value and has been proven to work well.

    Yours,

    Peter Myerscough-Jackopson

  • 0 in reply to Peter Myerscough-Jackopson
    Genius 5040 points

    Hi Peter,

    The INDEX register is needed only to configure each FIFO in USB0 peripheral on the c674x.  It maps each PERI_XXXXX to its own address space. Otherwise, why would sending over EP2 work after sending over EP1?

    Unfortunately we are too far down the road to change libraries.

    From what I can tell from the documentation and examples, sending and receiving is very simple at the chip level after setup. Fill FIFO, set TXPCKRDY, IRQ when sent, FIFO fills, IRQ data available, Fill FIFO, set TXPCKRDY, IRQ when sent, etc.  What additional information is needed to suggest the problem?

    Kurt

  • 0 in reply to Kurt Jensen
    Genius 5040 points

    The blues is an interesting genre.  Most of it is about stuff dat go wrong, but a lot of it includes what happen when da sun shine on me

    Turns out the PC -was- getting the return value. But what was sent was wrong so it got stuck...mea culpa