Using cache clean and invalidate functions with industrial SDK 1.0.0.4 examples

Darrin Hansen

Other Parts Discussed in Thread: SYSBIOS

I have a project that I am basing on the straight-forward tiescappl.c (EtherCAT) example project in the 1.0.0.4 SDK. In my extension of this project, I am using the EDMA to read/write via SPI to an external device. All is basically working but I have stumbled onto cache coherency issues with the SPI read and write buffers (basically the same issue/warning detailed in the uartEdam_Cache.c starterware example file). So in order to ensure coherency, I am calling CacheDataCleanBuff() and CacheDataInvalidateBuff() at the appropriate times on the transmit and receive DMA buffers, respectively. To my understanding, these cache manipulation functions are contained in the system.lib file located in C:\ti\am335x_sysbios_ind_sdk_1.0.0.4\sdk\starterware\binary\armv7a\cgt_ccs\am335x\system_config, and I have therefore included that library into the project linker configuration. However, the link phase now fails with the error:

fatal error: file

"C:\ti\am335x_sysbios_ind_sdk_1.0.0.4\sdk/starterware/binary/armv7a/cgt_ccs/am335x/system_config/system.lib<cache.obj>" was built without VFP

coprocessor support while a previously seen file was; combining incompatible files

My questions are:

1. Am I indeed using the correct (i.e. only) library files for these cache manipulation functions?

2. If #1 is correct, then is the only recourse to eliminate this error that I must rebuild system.lib so that cache.obj has VFP support? (as it seems that apparently other libraries being referenced by the EtherCAT example project were compiled with VFP support?)

3. If #2 is correct, are there any precautions or procedures to help me in performing this rebuild procedure? (I am concerned about "breaking" cache.obj, and cache manipulation is one spot I certainly don't want to mess up as it could be one of those bugs that doesn't always manifest itself consistently... kind of like stack overrun issues).

Thanks,

Darrin

over 13 years ago

0 Sujith KV over 13 years ago

TI__Intellectual 2525 points

Hi Darrin,

1. Yes, You are using the correct library files for cache maintanance operations.

2. Ok. By default, system config library is not built with VFP support. You may rebuild and check the same

3. There is an issue in the APIs CP15DCacheCleanBuff and CP15DCacheFlushBuff, which are internally used by CacheDataCleanBuff() and CacheDataInvalidateBuff() respectively. You can replace them with the below pasted code in /system_config/armv7a/cgt/cp15.asm. Anyway, this will be available in the next StarterWare release, StarterWare 02.00.00.07.

CP15DCacheCleanBuff:
    PUSH    {r14}
    ADD     r14, r0, r1               ; Calculate the end address
    DMB
    MRC     p15, #0, r2, c0, c0, #1   ; Read Cache Type Register
    UBFX    r2, r2, #16, #4           ; Extract the DMinLine
    MOV     r3, #2
    ADD     r3, r3, r2
    MOV     r2, #1
    LSL     r2, r2, r3                ; Calculate the line size

    SUB     r3, r2, #1                ; Calculate the mask
    BIC     r0, r0, r3                ; Align to cache line boundary
    TST     r3, r14
    BIC     r14, r14, r3
    MCRNE   p15, #0, r14, c7, c10, #1 ; Clean D/Unified to PoC by MVA

cleanloop:
    MCR     p15, #0, r0 , c7, c10, #1 ; Clean D/Unified to PoC by MVA
    ADDS    r0, r0, r2                ; Go to next line
    CMP     r0, r14
    BLT     cleanloop

    POP     {r14}
    DSB
    BX      lr

CP15DCacheFlushBuff:
    PUSH    {r14}
    ADD     r14, r0, r1               ; Calculate the end address
    DMB
    MRC     p15, #0, r2, c0, c0, #1   ; Read Cache Type Register
    UBFX    r2, r2, #16, #4           ; Extract the DMinLine
    MOV     r3, #2
    ADD     r3, r3, r2
    MOV     r2, #1
    LSL     r2, r2, r3                ; Calculate the line size

    SUB     r3, r2, #1                ; Calculate the mask
    TST     r3, r0
    BIC     r0, r0, r3                ; Align to cache line boundary
    MCRNE   p15, #0, r0, c7, c14, #1 ; Clean and Flush D/U line to PoC
    ADDNE   r0, r0, r2
    TST     r3, r14
    BIC     r14, r14, r3
    MCRNE   p15, #0, r14, c7, c14, #1 ; Clean and Flush D/U line to PoC
    B       dflushcmp

dflushloop:
    MCR     p15, #0, r0 , c7, c6, #1 ; Flush D/U line to PoC
    ADDS    r0, r0, r2                ; Go to next line

dflushcmp:
    CMP     r0, r14
    BLT     dflushloop
    POP     {r14}
    DSB
    BX      lr

Regards,

Sujith.

0 Darrin Hansen over 13 years ago in reply to Sujith KV

Intellectual 810 points

Sujith -

Thanks so much for your help - I made the modifications to CP15.ASM that you suggested and recompiled system.lib with VFPv3 support. Now my project compiles successfully and all appears to be in order with respect to cache coherence.

Regards,

Darrin

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Using cache clean and invalidate functions with industrial SDK 1.0.0.4 examples