uPP throughput

dp,

Can you provide me with a document # or URL which has this statement?  I'd like to see if there's some context to go along with this comment. 

That said, it will operate continuously at 75MHz on the Keystone devices.

Best Regards,
Chad

Chad,

The reference is http://focus.ti.com.cn/download/trng/multimedia/dsp/OLT109058/upp_intro/upp_intro_small.html 

page 2: uPP at a Glance "Up to 120MB/s (sustained throughput) per channel"

Regards,

dp 

Though the presentation is for a different family of devices, the general principles would hold true.  If you go further into the presentation it does meantion the Max Theoretical at being 150MB/s while the measured performance being 120MB/s.  It would still be operating at 75MHz clocking rate to achieve the 120MB/s actual sustained throughput.

The next revision of our Throughput Performance Guide should also include uPP measured performance data.

Best Regards,

Chad

Chad,

Thanks for your reply.

Could you please explain how to archive 120MB/s at 75MHz clocking rate ?

Need the FPGA send data in frames intermittently like below?  

____|————|____| ———— |____|————|____ 

If so,  what should the duty ratio be set?

Regards,

dp 

dp,

I'm not sure exactly what you're asking for.  The theoretical throughput is 150MB/s, the actual achievable sustained throughput do to overhead is 120MB/s.

Best Regards,

Chad

Chad，

I don't know what's the overhead and timing of uPP.

In my opinion, if the uPP works at 75MHz and the CH_ENABLE keeps valid, EDMA3 fetch data on fifo threshold quickly enough. So where does the overhead come from ?

If there is overhead, does that mean the CH_ENABLE cannot be valid all the time ? then what should it be ? 

Regards,

dp 

No, the CH_ENABLE could not be held active all the time.  This should be evident by the timing diagram.  You will not be able to maintain a constant data transmission on every single cycle, there is overhead between blocks of data being transmitted or received.

Best Regards,

Chad

Chad,

In TI's document view, uPP is very similar with Video Port.

The video port's bandwith could be calculated by clcok rate x date width without overhead.

If uPP has overhead, how should the timing diagram be ? How long the blocks be and how long should the overhead be in timing diagram ? How long should the CH_ENABLE be held inactive ? 

Regards,

dp 

dp,

Please see the timing diagrams for related timing information. 

Best Regards,

Chad