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SIO_reclaim for output stream in MCBSP hangs.

Other Parts Discussed in Thread: OMAPL138

I am working on OMAPL138 to develop a voip solution. I am using the mcbsp to transmit and receive the data simultaneously in multichannel mode. OMAP is in slave mode and receiving clock and frame sync externally, clock being at 4 MHZ. Number of channels used is 64.

The issue i am facing is that the SIO_reclaim for mcbsp output stream hangs with the following configuration for 64 channels although it works fine for 32 channels.

/*    *    *Mcbsp tx channel confiugration*    *    */

Mcbsp_DataConfig mcbspChanConfigtx =
{
    Mcbsp_Phase_SINGLE,
    Mcbsp_WordLength_8,
    Mcbsp_WordLength_8,    /* Dont care for single phase*/
    NUM_OF_CHANNELS,
    NUM_OF_CHANNELS,    /* Dont care for single phase*/
    Mcbsp_FrmSync_DETECT,
    Mcbsp_DataDelay_0_BIT,
    Mcbsp_Compand_ALAW,
    Mcbsp_BitReversal_DISABLE,
    Mcbsp_IntMode_ON_SYNCERR,
    Mcbsp_RxJust_RZF,    /* Dont care for TX         */
    Mcbsp_DxEna_OFF
};


/**< clock setup for TX section */
Mcbsp_ClkSetup mcbspClkConfigtx =
{
    Mcbsp_FsClkMode_EXTERNAL,
    8000,                        /*8Khz*/
    Mcbsp_TxRxClkMode_EXTERNAL,
    Mcbsp_FsPol_ACTIVE_HIGH,        
    Mcbsp_ClkPol_RISING_EDGE       
};


/**< Multi channel setup                                                      */
Mcbsp_McrSetup mcbspMultiChanCtrltx =
{
    Mcbsp_McmMode_ALL_CHAN_ENABLED_MASKED,
    Mcbsp_PartitionMode_CHAN_0_15,
    Mcbsp_PartitionMode_CHAN_16_31,
    Mcbsp_PartitionMode_8
};

Mcbsp_ChanParams mcbspChanparamtx =
{
    Mcbsp_WordLength_16,        /* wordlength configured    */
    NULL,                        /* loop job buffer internal */
    0,                            /* user loopjob length      */
    NULL,                        /* global error callback    */
    NULL,                        /* edma Handle              */
    1,                            /* EDMA event queue         */
    8,                            /* hwi number               */
    Mcbsp_BufferFormat_MULTISLOT_INTERLEAVED,
    TRUE,                        /* FIFO mode enabled        */
    &mcbspChanConfigtx,            /* channel configuration    */
    &mcbspClkConfigtx,            /* clock configuration      */
    &mcbspMultiChanCtrltx,        /* multi channel control    */
    0xffffffff,                
    0xffffffff,
    0x00,
    0x00
};

/* Mcbsp rx channel configuration*/
Mcbsp_DataConfig mcbspChanConfigrx =
{
    Mcbsp_Phase_SINGLE,
    Mcbsp_WordLength_8,
    Mcbsp_WordLength_8,    /* Dont care for single phase*/
    NUM_OF_CHANNELS,
    NUM_OF_CHANNELS,    /* Dont care for single phase*/
    Mcbsp_FrmSync_DETECT,
    Mcbsp_DataDelay_0_BIT,
    Mcbsp_Compand_ALAW,
    Mcbsp_BitReversal_DISABLE,
    Mcbsp_IntMode_ON_SYNCERR,
    Mcbsp_RxJust_RZF,    /* Dont care for TX         */
    Mcbsp_DxEna_OFF
};

/**< clock setup for TX section                    */
Mcbsp_ClkSetup mcbspClkConfigrx =
{
    Mcbsp_FsClkMode_EXTERNAL,
    8000,                        /*8khz */
    Mcbsp_TxRxClkMode_EXTERNAL,
    Mcbsp_FsPol_ACTIVE_HIGH,        
    Mcbsp_ClkPol_RISING_EDGE,    /*it must be Falling edge for Rx channel*/
};

/**< Multi channel setup                                                      */
Mcbsp_McrSetup mcbspMultiChanCtrlrx =
{
    Mcbsp_McmMode_ALL_CHAN_ENABLED_MASKED,
    Mcbsp_PartitionMode_CHAN_0_15,
    Mcbsp_PartitionMode_CHAN_16_31,
    Mcbsp_PartitionMode_8
};

Mcbsp_ChanParams mcbspChanparamrx =
{
    Mcbsp_WordLength_16,    /* wordlength configured    */
    NULL,                    /* loop job buffer internal */
    0,                        /* user loopjob length      */
    NULL,                    /* global error callback    */
    NULL,                    /* edma Handle              */
    1,                        /* EDMA event queue         */
    8,                        /* hwi number               */
    Mcbsp_BufferFormat_MULTISLOT_INTERLEAVED,
    TRUE,                    /* FIFO mode enabled        */
    &mcbspChanConfigrx,        /* channel configuration    */
    &mcbspClkConfigrx,        /* clock configuration      */
    &mcbspMultiChanCtrlrx,    /* multi channel control    */
    0xffffffff,
    0xffffffff,
    0x00,
    0x00
};

Could anybody please guide me on this. Whether my configuration of the mcbsp is incorrect or there could be some other problem.

  • Hi Pankaj,

    I guess you are using the BIOS PSP 1.30.01 release. Am I right?

    If you look at the word length configuration, there is conflict in "mcbspChanConfigtx" and "mcbspChanparamtx". Could please correct it? (Same for receive configuration)

    Pankaj Bamola said:
    /**< Multi channel setup                                                      */
    Mcbsp_McrSetup mcbspMultiChanCtrltx =
    {
        Mcbsp_McmMode_ALL_CHAN_ENABLED_MASKED,
        Mcbsp_PartitionMode_CHAN_0_15,
        Mcbsp_PartitionMode_CHAN_16_31,
        Mcbsp_PartitionMode_8
    };

    Could you please replace "Mcbsp_McmMode_ALL_CHAN_ENABLED_MASKED" with "Mcbsp_McmMode_ALL_CHAN_ENABLED_UNMASKED"? (Same for receive configuration)

    Let me know the result.

    Thanks and Regards,

    Sandeep K

  • Hi Sandeep,

    My sincere apologies for the delayed response.

    Below are the answers to your queries:

    • I guess you are using the BIOS PSP 1.30.01 release. Am I right?

     Yes, i am using BIOS PSP 1.30.01.

    • If you look at the word length configuration, there is conflict in "mcbspChanConfigtx" and "mcbspChanparamtx". Could please correct it? 

    I am using the Mcbsp_Compand_ALAW option in the mcbspChanConfigtx as well as mcbspChanConfigrx and hence am using different word length configurations  in "mcbspChanConfigtx" and "mcbspChanparamtx"(as it should be as per my understanding).

    • Could you please replace "Mcbsp_McmMode_ALL_CHAN_ENABLED_MASKED" with "Mcbsp_McmMode_ALL_CHAN_ENABLED_UNMASKED"? (Same for receive configuration).

     As per my understanding and SPRUH77A (Please correct me if i am wrong) , Mcbsp_McmMode_ALL_CHAN_ENABLED_MASKED option will prevent the transmission from being completed(DX pin is held in the high-impedance state; data cannot be shifted out on the DX pin.) and the transmission could be completed only on the channels enabled in the XCEREn and RCEREn registers (which i have done).

    However, I acted as per your advice and it still doesnt work out. The issue remains same as before.

    Thanks for your co-operation.

  • Hi pankaj,

    Can you please share the Mcbsp register dump just before invoking "SIO_reclaim()"?

    Regards,

    Sandeep K