HI,
I am using the BIOS_PSP package version, biospsp_03_10_05_00 for my McASP interface driver in DSP.
I have changed the Clock and Frame Sync configuration according to my Custom board setup. Following are the major changes:
1. McASP is the Master
2. We are using External AHCLKX input clock to generate ACLKX
3. McASP0 is used , Serializer 0 - TX and 4 - RX
Following is the Register Setting done for the above changes: Following is the Reg Dump Before Enabling the DMA Transfer:
[C674X_0] (hMcasp->regs)->PFUNC = 0
[C674X_0] (hMcasp->regs)->PDIR = b400000f
[C674X_0] (hMcasp->regs)->PDOUT = 1
[C674X_0] (hMcasp->regs)->PDIN = 0
[C674X_0] (hMcasp->regs)->PDCLR = 0
[C674X_0] (hMcasp->regs)->GBLCTL = 300
[C674X_0] (hMcasp->regs)->AMUTE = 0
[C674X_0] (hMcasp->regs)->DLBCTL = 0
[C674X_0] (hMcasp->regs)->DITCTL = 0
[C674X_0] XSTAT = 10c
[C674X_0] XGBLCTL = 300
[C674X_0] XMASK = ffffffff
[C674X_0] XFMT = 18074
[C674X_0] AFSXCTL = 82
[C674X_0] ACLKXCTL = bf
[C674X_0] AHCLKXCTL = 0
[C674X_0] XTDM = 1
[C674X_0] XINTCTL = 20
[C674X_0] (hMcasp->regs)->XSLOT = 17f
[C674X_0] (hMcasp->regs)->XCLKCHK = 86000000
[C674X_0] (hMcasp->regs)->XEVTCTL = 0
[C674X_0] (hMcasp->regs)->SRCTL0 = 11
[C674X_0] (hMcasp->regs)->XBUF0 = 0
[C674X_0] (hMcasp->fifoRegs)->WFIFOCTL = 10101
[C674X_0] (hMcasp->fifoRegs)->WFIFOSTS = 0 /* FIFO is Filled with Data */
[C674X_0] (hMcasp->fifoRegs)->RFIFOCTL = 1004
[C674X_0] (hMcasp->fifoRegs)->RFIFOSTS = 0
Following are the EDMA Register settings for Event Register and Interrupt register
[C674X_0] ER = 100
[C674X_0] ESR = 0
[C674X_0] EER = 0
[C674X_0] EESR = 0
[C674X_0] IER = 100
[C674X_0] IERH = 0
[C674X_0] IPR = 0
[C674X_0] IPRH = 0
After DMA is Enabled,
[C674X_0] Mcasp_localLoadPktToEdma():After ENABLE TRANSFER....
[C674X_0] MODULEMODE = 2
[C674X_0] (hMcasp->regs)->PFUNC = 0
[C674X_0] (hMcasp->regs)->PDIR = b400000f
[C674X_0] (hMcasp->regs)->PDOUT = 1
[C674X_0] (hMcasp->regs)->PDIN = 4000000
[C674X_0] (hMcasp->regs)->PDCLR = 0
[C674X_0] (hMcasp->regs)->GBLCTL = 300
[C674X_0] (hMcasp->regs)->AMUTE = 0
[C674X_0] (hMcasp->regs)->DLBCTL = 0
[C674X_0] (hMcasp->regs)->DITCTL = 0
[C674X_0] XSTAT = 10c
[C674X_0] XGBLCTL = 300
[C674X_0] XMASK = ffffffff
[C674X_0] XFMT = 18074
[C674X_0] AFSXCTL = 82
[C674X_0] ACLKXCTL = bf
[C674X_0] AHCLKXCTL = 0
[C674X_0] XTDM = 1
[C674X_0] XINTCTL = 20
[C674X_0] (hMcasp->regs)->XSLOT = 17f
[C674X_0] (hMcasp->regs)->XCLKCHK = 86000000
[C674X_0] (hMcasp->regs)->XEVTCTL = 0
[C674X_0] (hMcasp->regs)->SRCTL0 = 11 /* Serializer Buffer is Empty */
[C674X_0]
[C674X_0] (hMcasp->regs)->XBUF0 = 0
[C674X_0] (hMcasp->fifoRegs)->WFIFOCTL = 10101
[C674X_0] (hMcasp->fifoRegs)->WFIFOSTS = 40 /* FIFO is Filled with Data */
[C674X_0] (hMcasp->fifoRegs)->RFIFOCTL = 1004
[C674X_0] (hMcasp->fifoRegs)->RFIFOSTS = 0
Taking McASP Out of reset one by one for Serializer, SM and FS
[C674X_0] XSTAT = 0x8
[C674X_0] Mcasp_localIsrSwiFxn....
[C674X_0]
[C674X_0] mcaspBitSetGblXCtl:(instHandle->hwInfo.regs)->GBLCTL=700
[C674X_0]
[C674X_0] mcaspBitSetGblXCtl:(instHandle->hwInfo.regs)->GBLCTL=f00
[C674X_0]
[C674X_0] mcaspBitSetGblXCtl:(instHandle->hwInfo.regs)->GBLCTL=1f00
After this step, The SRCTL0 is chnaged to 1 (indicating data is there in Buffer). Following is the Reg Dump:
[C674X_0] (hMcasp->regs)->PFUNC = 0
[C674X_0] (hMcasp->regs)->PDIR = b400000f
[C674X_0] (hMcasp->regs)->PDOUT = 1
[C674X_0] (hMcasp->regs)->PDIN = 4000000
[C674X_0] (hMcasp->regs)->PDCLR = 0
[C674X_0] (hMcasp->regs)->GBLCTL = 1f00
[C674X_0] (hMcasp->regs)->AMUTE = 0
[C674X_0] (hMcasp->regs)->DLBCTL = 0
[C674X_0] (hMcasp->regs)->DITCTL = 0
[C674X_0] XSTAT = 175
[C674X_0] XGBLCTL = 1f00
[C674X_0] XMASK = ffffffff
[C674X_0] XFMT = 18074
[C674X_0] AFSXCTL = 82
[C674X_0] ACLKXCTL = bf
[C674X_0] AHCLKXCTL = 0
[C674X_0] XTDM = 1
[C674X_0] XINTCTL = 20
[C674X_0] (hMcasp->regs)->XSLOT = 0
[C674X_0] (hMcasp->regs)->XCLKCHK = 85000000
[C674X_0] (hMcasp->regs)->XEVTCTL = 0
[C674X_0] (hMcasp->regs)->SRCTL0 = 1 /* Serializer Buffer is Full */
[C674X_0]
[C674X_0] (hMcasp->regs)->XBUF0 = 0
[C674X_0] (hMcasp->fifoRegs)->WFIFOCTL = 10101
[C674X_0] (hMcasp->fifoRegs)->WFIFOSTS = 40
[C674X_0] (hMcasp->fifoRegs)->RFIFOCTL = 1004
[C674X_0] (hMcasp->fifoRegs)->RFIFOSTS = 0
Here i am getting Underrun in XSTAT Register. But the FIFO Status is showing there is data in the FIFO. What does it mean?
Also i am not getting any DMA Completion callback for the first transfer, indicating the First DMA request itself is waiting for the AXEVT from McASP.
The observation on the McASP output is ACLKX and AFSX output is coming properly (256K & 16K), But the DATA output is not coming...
I also verified the PWRM Register, CM_ALWON_MCASP0_CLKCTRL for McASP module Status. MODULEMOD in CM_ALWON_MCASP0_CLKCTRL @ 0x08181540 is giving 0x02 (indicating - ENABLE: Module is explicitly enabled. Interface clock may be gated according to the clock domain state.
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen.).
Note: The McASP control register setting is same as the working McASP driver from ARM side.
Thank you very much if you can guide me to resolve this issue.
Thanks and Regards,
Ansa Ahammed.