PLL lockup issue & IBL workflow

Take I2C POST boot as example.

Reference: http://processors.wiki.ti.com/index.php?title=BIOS_MCSDK_2.0_User_Guide#Intermediate_Boot_Loader_.28IBL.29_and_Examples

My questions are texts in red color.

The booting procedure is as follows.

1. FPGA samples the bootmode pins
   For I2C POST boot, DEVSTAT need value 0x0000 000B. However, the value will NOT be updated to DEVSTAT immediately.
   It will be stored in a register in FPGA.
   It is found in EVM that the initial value of DEVSTAT is not 0x0000 000B, but 0x0000 080B
    
2. FPGA forces the DSP to boot via I2C bus address 0x51
   How to force?  Write 0x0000080B to DEVSTAT directly? Through SPI?
    
3. PLL is initialized correctly by the IBL on the I2C.
4. IBL reads the sampled bootmode from an FPGA register.
   Is it a SPI reading?
    
5. IBL checks the bootmode, if it is not I2C boot or it is I2C boot but with bus address 0x50, IBL writes bootmode into the DEVSTAT register
6. Re enter RBL
   ...... 
   
   

Thanks.

 Boll