DM8168 CLKOUT signal

Hi Maril,

Reading the DM816x TRM together with the linux code (file clock816x_data.c), I see that to get a 27 MHz clock on the CLKOUT pin, you do not need to modify the Flying Synthesizer or sysclk11,17,16. The Video PLL clk1 is sourced from the sys_clk:

/sys_clkin_ck/video_pll_clk1_ck - the sys_clkin_ck is 27 MHz, the video_pll_clk1_ck is 216 MHz. 

You need to modify the CM_CLKOUT_CTRL register (offset 0x100) as follows:

1. [7] CLKOUT2EN = 0x1 - enable the clock out signal

2. [2:0] CLKOUT2SOURCE = 0x2 - select video_pll_clk1_ck

3. [5:3] CLKOUT2DIV = 0x3 - select /8 (216/8 = 27)

Also make sure that you have selected the CLKOUT signal on the device pin: PINCTRL320[2:0] MUXMODE = 0x0 (CLKOUT), address 0x48140CFC.

This should be enough to drive the CLKOUT pin output with 27 MHz.

Best regards,

Pavel

Hi Pavel ,

Thanks for the detailed reply .If i understand correctly than the clock marked in the below figure is routed to CLKOUT. We need a stable 27 MHz clock on clockout pin . From the figure below it appears that the clockout would vary if we modify any one of P,N, FREQ1 values . Is my understanding correct ? How can we ensure that clkout is stable even when we update video PLL parameters ?

In our system we have the following values programmed for video PLL

P = 2, N=110, FREQ1 = 13.75 Fr=27 MHz.

In such case video PLL clk1 should be 27*8*110/(2*13.75) = 864

We programmed the CM_CLKOUT_CTRL to 0x9a

 1. [7] CLKOUT2EN = 0x1 - enable the clock out signal

2. [2:0] CLKOUT2SOURCE = 0x2 - select video_pll_clk1_ck

3. [5:3] CLKOUT2DIV = 0x4 - select /16

We expected to see a 54 MHz clock (i.e 864/16 ) But we see an unstable clock of varying frequency. Do you have any clue what could be wrong here. As you had suggested we have ensured that pincontrol register is configured properly.

-Anil

Hi Maril,

You state that your video PLL clock 1 is 864 MHz. But in DM816X datasheet (sprs614b.pdf), Table 7-13. PLL Clock Frequencies shows that the max frequency of video PLL clock 1 is 660 MHz. I think this is the issue to be solved.

Also make sure that you have locked the video PLL once you are done with the configurations (section 7.3.4.3 PLL Locking Sequence).

BR,

Pavel

Hi Pavel ,

I have a confusion in calculating the value of video pll clk1 from P,N and FREQ values as this information is not very clear from datasheet .Can you confirm if this equation is correct

video pll clk1 = (fr * N * K)/(P * freq1) ?

In our case N =110, P=2 , Fr=27 MHz and freq1=13.75

from this we get video PLL clk1 to be 864 MHz.

-Anil

Hi Anil,

I think that you are missing the M parameter in the equation: video pll clk1 = (fr * N * K)/(P * freq1 * M)

This is the formula in datasheet (SPRS614B – MARCH 2011 – REVISED FEBRUARY 2012), section 7.3.4 PLLs

This formula is double confirmed also in the TRM (http://www.ti.com/lit/pdf/SPRUGX8), section 1.10.3 Flying Adder PLL

Please examine careful the following sections in the TRM: 1.10.3.1.3 Video PLL, table 1-83. Example for Video PLL Frequencies, 1.10.3.1.3.1 Steps for Changing VIDEOPLL Frequency

BR,

Pavel

Hi Pavel ,

I intentionally removed the M parameter from my equation. This is because video PLL clk1 is tapped out before the divider. Please refer the figure I attached earlier . Please let me know if there is any mistake in my understanding.

P.S . I accidentally marked the post as answered. Please ignore the update.

-Anil

Hi Anil,

I rejected the verification of the post.

From my understanding, the M parameter (post divider) should participate in the formula. The dividers in the figure above are the PRCM dividers, not the PLL M post divider. The PRCM dividers are /A and /D1, programmed in the PRCM registers CM_SYSCLK11_CLKSEL and CM_VPD1_CLKSEL.

The PLL M post divider is programmed in the Control Module register VIDEOPLL_DIV1.

BR,

Pavel

Hi Pavel ,

OK. Which of the dividers(/A or /D1) should i consider for calculating video PLL clk1 frequency value ?

-Anil

Hi Anil,

None of these PRCM dividers (/A or /D1) should be considered for calculating video PLL clk1 frequency value. These should be considered when calculating sysclk11/16/17 frequency values.

My idea in my previous post is that you should consider the /M PLL post divider for calculating the video PLL clk1 frequency value.

BR,

Pavel

Hi Pavel ,

Oh OK. Sorry for my misunderstanding. In our system the parameters are as below :

N= 110, P=2 , M=4 , FREQ1 = 13.75

So video PLL CLK1 in our case = 27 * 110 * K/(2 * 4* 13.75)

for K=8 video PLL clk1 = 216 .

is my calculation correct ?

In this case if i programm CLKOUT_CTRL register to select video PLL clk1 and a divider value of 8 i should get 27 MHz  on clkout ?

-Anil

Hi Anil,

Yes, this looks correct to me. Please try and let me know if you still have issues with this.

BR,

Pavel

Hi Pavel ,

I tried these settings. However i see a 54 MHz output on clkout pin instead of 27 MHz. Also if i change the divider value in CLKOUT_CTRL to 16 (from my previous value of 8) to get a 27 MHz output i see a 43.1 MHz clock output ! Not sure why this is hapenning .

Reverifying my settings to confirm that my observations .

-Anil

Hi Anil,

Could you send me the values of the following registers:

1. VIDEOPLL_CTRL
2. VIDEOPLL_PWD
3. VIDEOPLL_FREQ1
4. VIDEOPLL_DIV1

BR,

Pavel

Hi Pavel ,

I am out of office. Since our office is shut down for maintenance whole of this week i shall provide you the grab of registers next week.

Thanks and regards,

-Anil

Hi Pavel ,

Sorry for the delayed respense. Here is the register values :

1. VIDEOPLL_CTRL - 0x6E0288
2. VIDEOPLL_PWD - 0x0
3. VIDEOPLL_FREQ1 - 0x8DC00000
4. VIDEOPLL_DIV1 - 0x104

-Anil

Hi Anil,

The VIDEOPLL_x registers settings looks correct.

When you have 54MHz clock signal on the CLKOUT pin, what is the value set in the CM_CLKOUT_CTRL[5:3] CLKOUT2DIV bitfield?

Also, can you try with these settings: CM_SYSCLK11_CLKSEL[0] CLKSEL = 0x1 and CM_CLKOUT_CTRL[5:3] CLKOUT2DIV = 0x0. Please let me know if this can provide 27MHz on the CLKOUT pin.

Best Regards,

Pavel

Hi Pavel ,

CM_CLKOUT_CTRL[5:3] = 0x3 to provide a divider value of 8 when i notice a 54 MHz clock.

I tried the setting mentioned by you CM_SYSCLK11_CLKSEL = 0x1 and CM_CLKOUT_CTRL[5:3] CLKOUT2DIV = 0x0 (CM_CLKOUT_CTRL = 0x82). With this change i am not able to see a stable clock on my CRO . I guess the clock frequency is above 100 MHz in this case and my CRO (which has a 100 MHz limit) is not able to capture it properly.

Also one more observation is that changes to CM_SYSCLK11_CLKSEL register does not affect the SYCLKOUT frequency. I observe a 54 MHz clock even when i programm CM_SYSCLK11_CLKSEL to 0x1

-Anil

Hi Anil,

This behaviour is strange for me also. May be we have a multiplier by 2, which is not documented. 

Can you try to modify the output clock from the Video PLL. My idea is to decrease it from 216MHz to 108MHz. In the u-boot, modify the M parameter:

#define VIDEO_MDIV1        0xA //0x5

You should keep CM_CLKOUT_CTRL[5:3] = 0x3.

Best Regards,

Pavel

Hi Pavel ,

Thanks for the info. We are now able to get a stable 27 MHz clock output . We programmed CLKOUT divider to 0x7 as suggested by you.

Thansk again ,

Anil