the SOC use is AM389X of TI with a Cortex A8 revision r3p2
board use : EVM AM389X of spectrum digital with a lauterbach tools
for testing L2 cache lockdown we are set the cache with the following parameter:
L1 inner policy : Noncacheable,nonbufferable
L2 inner policy : Cacheable,write-through, no write-allocate
we use the following algorithm
- unlock all way
- fill the way 0 to way 7 ( via PLE ) with the data located to 0x80A00000-0x80A40000 .So in the way0 , we have the data 0x80a00000-0x80a08000 and way 7 the data 0x80a38000-0x80A40000
- lock all the way ( 0- 7)
- check the data by a reading loop are located in L2 with performance monitor ( event 0x44(L2 MISS) ,0x45(AXI read) & 0x46 ( AXI write) = 0 )
until this point , all test are right
Now in our programm , we read the data 0x80a040000 to 0x80A48000 and just after 0x80a000000 to 0x80A08000 .
if we check the event 0x44, 0x45 during the reading phase for both , we have
0x80a040000 to 0x80A48000 - 0x44=512 , 0x45=2048
0x80a000000 to 0x80A08000 - 0x44=512 , 0x45=2048
if we read the data 0x80a048000 to 0x80A50000 and just after 0x80a000000 to 0x80A08000 , the we have the result
0x80a048000 to 0x80A50000 - 0x44=512 , 0x45=2048
0x80a000000 to 0x80A08000 - 0x44=512 , 0x45=2048
it seem that the data in WAY0 are evicted although the WAY0 is locked .
workaround : keep way 7 or way 0 not locked
We has searched in Cortex A8 documentation and in the forum , but we don't find any limitation or note about this issue
question : Can we lock the 8 way if our code access data or code outside data/code locked or we keep one way free to avoiding the data eviction or using lock the TLB ?
