DMA: hardware vs software interrupt

Cory Hansen said:

When implementing any of the DMA request lines (sys_ndmareq[3..0]) on the DM3730, does this interrupt go directly to the DMA controller to process the next frame of data (entirely within hardware) or does it interrupt software?  Then software intervenes by setting registers in the DMA controller.   The TRM seems to suggest this but maybe we are misinterpreting?  I would want to believe these interrupts stay with hardware for maximum speed and efficiency of the DMA.

I would like to understand where within the TRM you are seeing indications of the sys_ndmareq[3..0] going to the interrupt controller for the ARM processor.  Please cite the areas.

To address your inquiry, the sys_ndmareq[3..0] signals are connected to the SDMA controller and feed into 4 of the 96 possible trigger inputs.  Please see Figure 11-1 of the TRM which provides an illustration.  The SDMA controller does generate interrupts to the ARM processor at the completion of the configured transfer.

Thank you for your response.   What we are really after is can we configure the SDMA controller for a very large transfer (e.g. 2MB) then have the sys_ndmareq lines start and stop this larger data transfer without any software involvement?  For example external hardware asserts sys_ndmareq line then SMDA pushes some subset of the data over GPMC.  External hardware then de-asserts sys_ndmareq for a brief period of time.  Once hardware is ready for more data, its re-asserts sys_ndmareq.  SDMA continues from where he is paused before.  So no software involvement (software interrupts) until the whole transfer is complete even though the SDMA controller is getting multiple hardware interrupts

Using the words "seems to suggest" was bad...its more that its unclear how this "hardware synchronize transfer" in the SMDA section really works.