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I2C module access in OMAP L138

Al Hollmann
Prodigy 10 points
Other Parts Discussed in Thread: AM1806, OMAP-L138

Hello everybody,

i use the I2C0 module in the L138 (actually AM1806) in master mode to access some peripheral ICs

(the I2C0 module is clocked with 25MHz, the ARM is clocked with 175MHz).

Up to now i have implemented it quick-and-dirty without interrupts, but with some wait loops, etc.

I want to make sure that, before i programm a new data transfer, the old data transfer is finished, so i am allowed to trigger a new data transfer.

Reading the ARDY bit in ICSTR doesn't help, because it seems to be invalid after programming the stop condition of the last transfer.

Reading the BB bit of the ICSTR doesn't work for me neither, because it seems that the ARM core goes on to fast, after i detect BB==0.

Using the ICRRDY and ICXRDY of the ICSTR also doesn't help. Bit if i try to initiate a new transfer without any wait, my system will hang.

Could this be a problem regarding the two different clock domains (ARM is too fast) ?

So how can i make sure, the I2C0 peripheral is ready for programming a new transfer?

Are there code examples availabe? (best would be with INT usage, or even with INT and DMA usage)

Thanks a lot in advance!! :-)

Al

  • 0
    Prodigy 75 points

    We use OMAP-L138 with interrupts, 456Mhz, cache enabled... and seem to have the same problem as you at I2C 100kHz.
    I used the following additional sequence to check if the transfer is really finished.
    But i found that by try and error !!

    In our software, the loop after all registers like BB showed finished, went up till maximum 10.

        #define I2C_CON       (0xA4)
        #define I2C_CON_STB   (1 << 11)  // Start byte mode (master mode only)
        #define I2C_CON_MST   (1 << 10)  // Master/slave mode
        for (loops=0; loops<100; loops++) {
          if ( (HWREG(i2c[instanceNum].regBaseAddr + I2C_CON) & (I2C_CON_STB|I2C_CON_MST)) == 0)
              break;
        }