In testing error conditions for my UART ISR routines I noticed a small problem in reliably clearing the OE and FE bits in the LSR for UART 2 in the AM1806.
The error condition is caused by the following method. In CCS I hit a break point to stop the CPU but I still have serial data coming in from an external device on UART 2. When the CPU is resumed the UART has an OE. The ISR for the UART is called but it fails to clear the OE bit and further interrupts from the UART are not observed. This ISR routine has worked on other UART's with no problems.
In the AM1806 Tech Ref Manual (section 29.3.8) it states that the OE bit will be cleared in the LSR when the CPU reads the contents of the LSR. This does not happen and once the OE or FE bits are set the reset of the bits does not always occur. I have the FIFO enabled at a depth of 1 byte. I have also tried reading the RBR until the FIFO is empty. That also does not always clear the OE flag.
How do you always clear the OE flag on the AM1806 UART's? What is the guaranteed way of clearing the OE and FE flags?
I have provided a snippet of the ISR code for the UART.
void UART2Isr()
{
/* This determines the cause of UART2 interrupt.*/
int_id = UARTIntStatus(UART2_REGS);
/* Clears the system interupt status of UART2 in AINTC. */
// Hwi_clearInterrupt(UART2_INT_NBR);
/* Checked if the cause is transmitter empty condition.*/
if(UART_INTID_TX_EMPTY == int_id)
{
.. Send new byte to THR
}
/* Check if the cause is receiver data condition.*/
if(UART_INTID_RX_DATA == int_id)
{
... Get new byte from RHR
}
/* Check if the cause is receiver line error condition.*/
if(UART_INTID_RX_LINE_STAT == int_id)
{
while(UARTRxErrorGet(UART2_REGS)) /* Reads UART LSR */
{
/* Read a byte from the RBR if RBR has data.*/
UARTCharGetNonBlocking(UART2_REGS);
}
}
}
