tms320c6678

Avinash,

Please have a look at the PLL UG and Data Manual.   They are both available on the product page TMS320C6678.

The GEL file has PLL routines within it, you can open the GEL file and find the routines, and modify them as necessary for your needs.

Best Regards,

Chad

Chad,

I have gone through both the PLL User Manual and TMS320C6678. But I can't find any thing how to calculate the multiplier, divider values of PLL. we are using system clock of 100Mhz and DDRCLK of 66.66Mhz. With reference from the TMS320C6678 data sheet pg.no 34 (2.5.3 PLL Boot Configuration Settings). I have taken system clock of 100Mhz and DDRCLK of MHz as input clock and calculated the multiplier and divider value from the above specified page.no. 

TMS320C6678 supports upto 1GHz and our DDR3 supports upto 800 MHz. 

The values i have calculated has been listed bellow. 

Hi,

About the Main PLL You can find more detail in TMS320C6678 (Rev-C) para.7.5 (page 131).

In figure 7-7 You can see that the postdiv is fixed at 2, and that the corepack clock is SYSCLK1 that have another stage with fixed div=1.

So, corepack_clock = (((in_clock / prediv ) * mult)  / 2  ) / 1, where the /2 and /1 are fixed.

In your case:  1GHz =  ((100MHz /1)*20) / 2 ]

Note that the values really written in the PLL register are always the calculated value -1, since, for instance PLLDIV = 0 -> div 1 (see PLL user Manual)

Hello,

I have gone through both the PLL User Manual and TMS320C6678. But I can't find any thing how to calculate the multiplier, divider values of PLL. we are using system clock of 100Mhz and DDRCLK of 66.66Mhz. With reference from the TMS320C6678 data sheet pg.no 34 (2.5.3 PLL Boot Configuration Settings). I have taken system clock of 100Mhz and DDRCLK of MHz as input clock and calculated the multiplier and divider value from the above specified page.no.

TMS320C6678 supports upto 1GHz and our DDR3 supports upto 800 MHz.

The values i have calculated has been listed bellow.

/* Main PLL: 100 MHz reference, 1GHz output */
ibl.pllConfig[ibl_MAIN_PLL].doEnable = 1;
ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
ibl.pllConfig[ibl_MAIN_PLL].postdiv = 2;
ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;

/* DDR PLL: 66.66 MHz reference, 800MHz DDR rate */
ibl.pllConfig[ibl_DDR_PLL].doEnable = 0;
ibl.pllConfig[ibl_DDR_PLL].prediv = 1;
ibl.pllConfig[ibl_DDR_PLL].mult = 24;
ibl.pllConfig[ibl_DDR_PLL].postdiv = 2;
ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz = 800;

can you just verify the values . If there is any formula to calculate the above values please mention it.
what should be the value for pllOutFreqMhz ,doEnable ,prediv ,postdiv ,mul for  Main PLL, DDR PLL? we are using DDR3 and the chip specification  is MT41J128M16HA-125 IT (micron chip).

First, please note that right now we're only supporting up to 1333MT/s (667MHz input clock) for DDR3 on C6678.  This is documented in the Errata.

I'm not an IBL expert, so I'm not sure if the code compensates for the fact that PLLM is the value programmed into the bitfield +1 (in other words needs to subtract one of the actual multiplier value and write this into the bit field.)  I'll ping someone who's knowledgable on the IBL to address that specifically.

On both PLL, IBL values, I'd suspect that you'd want the doEnable to be set to one for both PLL's.  You'd want it so that the actual PLLM bitfield is set to 19 (so x20 is the actual multiplication), the PLLD to be set to 0 (so that x1 is the actual divisor) and the postdiv should actually be fixed as /2.  It's probably added into the IBL just so you can see it clearly.

So, that looks like it may be correct, but you can always probe the SYSCLKOUT pin which will have the SYSCLK / 6 as the output.

The same above holds true on the DDR PLL.  And you'd actually program it to the same values since you'll want the end multiplication factor to be 10x. 

Best Regards,
Chad

Merged threads - Let's try to keep this as one thread.

Thanks and Regards,

Chad

Hi,

I got a clear idea now. what are the register that should be configured for proper operation. I have listed the registers can you let me know  what registers should be configured and why?

I have a in source file in that certain register are configured and certain registers are assumed as 0. Can you just let me know why?

I have attached that in this mail.

ibl.ddrConfig.configDdr = 1;
    ibl.ddrConfig.uEmif.emif4p0.registerMask = ibl_EMIF4_ENABLE_sdRamConfig | ibl_EMIF4_ENABLE_sdRamRefreshCtl | ibl_EMIF4_ENABLE_sdRamTiming1 | ibl_EMIF4_ENABLE_sdRamTiming2 | ibl_EMIF4_ENABLE_sdRamTiming3 | ibl_EMIF4_ENABLE_ddrPhyCtl1;

    ibl.ddrConfig.uEmif.emif4p0.sdRamConfig                = 0x63C452B2;
    ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2            = 0;
    ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl            = 0x000030D4;
    ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1            = 0x0AAAE51B;
    ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2            = 0x2A2F7FDA;
    ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3             = 0x057F82B8;
    ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1            = 0;
    ibl.ddrConfig.uEmif.emif4p0.powerManageCtl            = 0;
    ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic            = 0;
    ibl.ddrConfig.uEmif.emif4p0.performCountCfg            = 0;
    ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel    = 0;
    ibl.ddrConfig.uEmif.emif4p0.readIdleCtl                = 0;
    ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet        = 0;
    ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg    = 0;
    ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg            = 0;
    ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1                 = 0x0010010d;
    ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2                = 0;
    ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap            = 0;
    ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map        = 0;
    ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map        = 0;
    ibl.ddrConfig.uEmif.emif4p0.eccCtl                    = 0;
    ibl.ddrConfig.uEmif.emif4p0.eccRange1                = 0;
    ibl.ddrConfig.uEmif.emif4p0.eccRange2                = 0;
    ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh            = 0;

Hi Chad,

I got a clear idea now. what are the register that should be configured for proper operation. I have listed the registers can you let me know  what registers should be configured and why?

I have a in source file in that certain register are configured and certain registers are assumed as 0. Can you just let me know why?

I have attached that in this mail.

ibl.ddrConfig.configDdr = 1;
    ibl.ddrConfig.uEmif.emif4p0.registerMask = ibl_EMIF4_ENABLE_sdRamConfig | ibl_EMIF4_ENABLE_sdRamRefreshCtl | ibl_EMIF4_ENABLE_sdRamTiming1 | ibl_EMIF4_ENABLE_sdRamTiming2 | ibl_EMIF4_ENABLE_sdRamTiming3 | ibl_EMIF4_ENABLE_ddrPhyCtl1;

    ibl.ddrConfig.uEmif.emif4p0.sdRamConfig                = 0x63C452B2;
    ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2            = 0;
    ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl            = 0x000030D4;
    ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1            = 0x0AAAE51B;
    ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2            = 0x2A2F7FDA;
    ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3             = 0x057F82B8;
    ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1            = 0;
    ibl.ddrConfig.uEmif.emif4p0.powerManageCtl            = 0;
    ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic            = 0;
    ibl.ddrConfig.uEmif.emif4p0.performCountCfg            = 0;
    ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel    = 0;
    ibl.ddrConfig.uEmif.emif4p0.readIdleCtl                = 0;
    ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet        = 0;
    ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg    = 0;
    ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg            = 0;
    ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1                 = 0x0010010d;
    ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2                = 0;
    ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap            = 0;
    ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map        = 0;
    ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map        = 0;
    ibl.ddrConfig.uEmif.emif4p0.eccCtl                    = 0;
    ibl.ddrConfig.uEmif.emif4p0.eccRange1                = 0;
    ibl.ddrConfig.uEmif.emif4p0.eccRange2                = 0;
    ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh            = 0;

Avinish,

There is documentation on the DDR3 interface on the TMS320C6678 product page.  I'd suggest going through the DDR3 User Guide and the DDR3 Initialization Application Note which can be found there and then coming back if you have specific questions.

Best Regards,

Chad

2500.DDR3_PHY.xlsxHi Chad,

     I want to know how to calculate the DQS routed length and clock routed length from the PCB length. there are two values in that is DQS and DQS# , In the clock we have two values for P and N value. How to calculate the values from this excel sheet.I have attached the excel sheet with this mail.

Regards,

Avinash

Avinash,

Tom addressed this on the other thread that you posted with the same question. Let's keep any follow ups regarding the trace lengths on that thread.

Best Regards,

Chad