C6748 PLL setup for DDR2

Hello,

PLLC0.SYSCLK2 is always half the CPU clock PLLC0.SYSCLK1. The division factor can be considered programmable (as any general PLL output), but since the only allowed value is 2...

The main DDR clock (MCLK) is generated from PLLC1.SYSCLK1, which is the source of the PHY output clock (DDR_CLK pins), typically 150 MHz. The DDR memory data transfer rate is then 600MB/s peak (300M 16-bit words per second).

Edit: PLLC1.SYSCLK1 itself runs at the DDR frequency (300MHz). The DDR controller user's guide is more explicit on clocks control.

Jakez

Thanks, that clarifies the PHY output clocking.

Is there any written documentation showing PLLC0.SYSCLK2 is always half of PLLC0.SYSCLK1?  The PLLC0 Divider 2 Register shows a default value of divide by 2 but does not seem to restrict the RATIO setting (0-1Fh). None of the documentation even shows SYSCLK2 being sourced from SYSCLK1. So the frequency of PLL0.SYSCLK2 does not have to be the same as PLL1.SYSCLK1 in driving the DDR controller? Is there a suggested ratio?

Also, with PLLC0.SYSCLK2 being set to PLLC0.SYSCLK1 divided by 2 would seem to directly effect the clocking of  things like UPP, SPI0, and others if I am reading figure 6-1 of SPRUGJ7E correctly.

By the way Figure 5-9 I referenced previously was in SPRS590D.

Another documentation question. Which is correct the CPU/Device column in Table6-2 for PLL0_AUXCLK or Figure 6-1 in SPRUH79A?

Dave,

In theTechnical Reference manual, Device clocking chapter (Chapter 7) of the Technical reference manual covers the relation between PLL0.SYSCLK1 and PLL0.SYSCLK2 and Table 7-2 documents that the relation ship between PLL0.SYSCLK1 and PLL0.SYSCLK2 is  fixed (ratio of 1:2 ). Diagram 8-1 in the Technical reference manual should clarify the question regarding how individual clock on the device are sourced.

The PLL controller section describes how the PLL clock dividers can be manipulated to obtain the required clocks for the peripherals. PLL0 SYSCLK2 is larger than the max speeds supported on SPI0 so  the peripheral provides a further programmable scaling factor called PRESCALE which is programmed in the SPIFMT register. Your interpretation of the PLL0 diagram is correct. SPI0 clocking will be affected by PLL0.SYSCLK1 variation. But C6748 also has a PLL1 interface where the SPI1 gets a clock from PLL1.SYSCLK2 which doesn`t have any clocking restrictions  so you could potential use SPI1.

The GEL file for any of the C6748 development platforms should be a good starting point for understanding how the DDR clocking is configured for example the EVM has mDDR on it and the GEL file demonstrates configuring it at 5 different frequency from 102Mhz  to 150 Mhz. The C6748 LCDK GEL shows similar configuration of DDR2.

Regards,

Rahul

PS: There is a similar discussion on the following forum thread that might interest you:

http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115/t/40085.aspx?Redirected=true

I am unable to open the links you provided. They give me a "Group not Found" error.

My bad. I have fixed the hyperlinks to point to the correct documents.

Regards,

Rahul