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Revision Identification

Gerard Belanger
Intellectual 800 points
Other Parts Discussed in Thread: SYSBIOS

Greetings!

I was reading through the Errata sprz360b. section 1.2, Revision identification.  I wrote come code (in a SYSBIOS app) to read and display the information referenced there.  I found a couple of discrepancies. 

1) The value read from the Main ID register was 0x413FC082.  According to the Main ID description in the ARM documentation, the Processor Variant is 3, and the Processor Revision is 2.  This does not appear to correlate the the value in Table 2 of the errata section which notes it as r3p2.  Maybe it should be listed as p3r2 in the table to go with the table heading for that column.

Did I interpret this correctly?  Is there any convenient way to distinguish variants of the am335x family in software?

2) The paragraph between Table 1 and Table 2 of the section says "The ROM code revision can be read from address 2BFFCh.".  I tried that, and got an exception.  I looked at the memory map for the AM335x in the TRM, and found the boot rom beginning at 0x40000000.  So I tried reading 0x4002BFFC.  That failed also. 

So the questions here are, is the boot rom really there, should it be readable, and if so, how?

I know I am picking nits here, but inquiring minds want to know.

Gerry Belanger

  • 0
    TI__Guru* 86180 points

    Gerard, your first question corresponds to the ARM Cortex-A8 revision.  I can't speak for ARM, but rXpX is how they represent Variant (rX) and Revision (pX).  AM335x will always have r3p2 Cortex-A8

    The best way to distinguish variant of AM335x is to look at DEVICE_ID register which will tell you silicon revision (as mentioned in the errata), and DEV_FEATURE, which will tell you which variant of the AM335x family you have (see Ch1 in the TRM)

    The ROM code also has a revision, which probably won't change unless a major bug is revealed.  I don't have an issue reading it from 0x2BFFC.  Be sure to just read that address, as reading 0x2C000 and beyond will give you an exception.

    Regards,

    james

  • 0 in reply to JJD
    Intellectual 800 points

    JJD,

    Thank you for the revision/variant explanation and reference to the other registers.

    The Rom revision was carelessness on my part.  But you provided the clue.  SYSBIOS is running with the data cache enabled.  So when I accessed the rom revision address, the chace line was read, running off the end of rom, and causing the exception.  I added an entry in the MMU table to make that region non-cacheable.  Problem solved.

    Thanks again!

    GerryB