DMTimer register write issue

Hi Christian,

Christian Lambricht said:

When I activate the CACHE_ALL in my code i get some strange behavior

I believe, I/O space is not made cacheble for exactly the same reason you are observing.

Since, I/O registers are prone to side effects (like self-clear-after-set, strict ordering requirements and so on), I/O register space should not be cached. Else, instead of seeing the actual values you may see the cached results. I hope I am right.

You should maintain a cache table and only enabling data caching on those regions that are not I/O mapped (in your case all the peripheral registers)

Christian Lambricht said:

My question is "Is it a normal behavior ???"

 I guess so.

 Thanks and regards,

Madhvapathi SRiram

Hello,

First, thank you for your reply.

Maybe your are right, I don't know but when I configure The DMTimer to use the 32KHz for the clock sourcing and when I disable all cache I have the same issue.

When I write to register and directly read, I don't have the value written..... I have to wait some times to view the correct value.

If you take a look at the platform code in Starterware (beaglebone or ) you will see that the code add some "while" to wait until the value is corectly written... Thus my question is why in the Drivers it is not the case. Why there is a different coding style between platform code and driver code?

Best regards,

Christian

Hi Christian,

The ''while'' loops present in the StarterWare platform's are not required and will be removed in the next release. On commenting the while loops in the StarterWare platform's the existing(default) dmtimer example application will work fine.

While loops in the driver are used, only when the Technical reference manual(TRM) says so(In this case not required). Adding while loops in every API/function will add overheads and reduce performance. Hence while loops are not used.

 Regards,

Jeethan

Hi Jeethan,

Try this, configure DMTimer to use 32KHz clock instead of 24MHz clock. Then write to prescaler register and directly read the value.... You will see that you will have to wait some time until the value is updated....That produce side effect when you don't wait with while :)

If you use the DMtimer in 24MHz you will have the same issue only if you active CACHE_ALL....

I don't know if I will have the same issue with the dmtimer example but this example never activates the CACHE_ALL.

Best regards,

Christian

Hi Christian,

I enabled the DMTimer pre-scaler counter and faced the similar issue with 32KHz input clock. The timer control register was not getting updated(TCLR).

This is because the POSTED mode of DMTimer is enabled by default(POSTED field of TSICR register is set). When POSTED mode is used software is supposed to poll for a bit before writing into TCLR register.

I polled for the "W_PEND_TCLR" field of Timer write posted status register(TWPS) and after that i enable and configure the prescaler clocks. It works.

Please try this configuration.

Regards,

Jeethan

Hi Christian,

Yes you are right.

Regards,

Jeethan