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RapidIO - C6472: what are the SRIO read time specs?

Eddie3909
Guru 10385 points

Hi

C6472

Our system is timing out on single word reads from the DSP SRIO port. We have an FPGA reading a DSP DDR2 word and sometimes the read time is over 500 usec before we get a response. Granted the DDR2 bus is busy because the DSP CPUs are crunching DDR2 data, but doesn't 500 usec for a single DDR2 word seem a bit excessive?

Are there ways to increase SRIO read priority in order to reduce how much time the FPGA stalls waiting on the DSPs DDR2 word response?

Cheers

  • 0
    TI__Expert 6815 points

    Eddie,

    What are the master priorities for SRIO and the DSP in your system? Are they the defaults or are you programming them with specific priority? If you reduce the CPU load on the DDR, does your response time improve (if this test is possible for you in your system)?

    If you believe there is some command starvation going on at the DDR2 controller, you also have the option of programming the Burst Priority Register (BPRIO). Here you can specify the number of memory transfers after which the controller raises the priority of the oldest command in the command FIFO. However, do keep in mind that it might lead to a corresponding decrease in the the DDR2 BW allocated to the DSP depending on the DSP loading of the DDR.