Hi,
We have a trouble at SPI slave boot on OMAPL-137.
uC fails a opcode handshake just after PLL is enabled by 0x5853590D opcode.
Condition:
Using 24.576Mhz X'tal.
Before PLL configuration, SPI clock is 100khz and 10ms software delay is being applied before and after each opcode handshake. And, we have 100usec delay between each 16bit word sequences. After PLL is configured, we have no delay for 16bit word sequences and SPI clock is changed to 16Mhz.
Rate of Boot failure with this condition:
1/1000
Advanced Debugging:
I tried to connect CCS and I found Program Counter was falling into strange address.
Also, I run the debug GEL (http://processors.wiki.ti.com/index.php/OMAP-L1x_Debug_Gel_Files) and then the following messages was displayed:
DSP_0: GEL Output: ---------------------------------------------
DSP_0: GEL Output: | Device Information |
DSP_0: GEL Output: ---------------------------------------------
DSP_0: GEL Output: DEV_INFO_00 = 0x14000100
DSP_0: GEL Output: DEV_INFO_01 = 0x9B7DF02F
DSP_0: GEL Output: DEV_INFO_02 = 0x00000000
DSP_0: GEL Output: DEV_INFO_03 = 0x0000F3F1
DSP_0: GEL Output: DEV_INFO_04 = 0x00000002
DSP_0: GEL Output: DEV_INFO_05 = 0x00000000
DSP_0: GEL Output: DEV_INFO_06 = 0x000003E0
DSP_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-155333-8-37-9
DSP_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 5,0,0,3422
DSP_0: GEL Output: -----
DSP_0: GEL Output: DEV_INFO_17 = 0x1ABC0000
DSP_0: GEL Output: DEV_INFO_18 = 0x00030003
DSP_0: GEL Output: DEV_INFO_19 =
DSP_0: GEL Output: 0
DSP_0: GEL Output: 0
DSP_0: GEL Output: 0
DSP_0: GEL Output: 0
DSP_0: GEL Output: 0
DSP_0: GEL Output:
DSP_0: GEL Output: -----
DSP_0: GEL Output: DEV_INFO_20 = 0x00030003
DSP_0: GEL Output: DEV_INFO_21 = 0x30303864
DSP_0: GEL Output: DEV_INFO_22 = 0x3330306B
DSP_0: GEL Output: DEV_INFO_23 = 0x00000000
DSP_0: GEL Output: -----
DSP_0: GEL Output: DEV_INFO_24 = 0x00000000
DSP_0: GEL Output: DEV_INFO_25 = 0x02009025
DSP_0: GEL Output: DEV_INFO_06 = 0x08025EC5
DSP_0: GEL Output: DEV_INFO_26 = 0x80100100
DSP_0: GEL Output:
DSP_0: GEL Output: ---------------------------------------------
DSP_0: GEL Output: | BOOTROM Info |
DSP_0: GEL Output: ---------------------------------------------
DSP_0: GEL Output: ROM ID: d800k-48-48-48
DSP_0: GEL Output: Silicon Revision UNKNOWN
DSP_0: GEL Output: Boot pins: 858796139
DSP_0: GEL Output: Boot Mode: INVALID (0x3330306B)
DSP_0: GEL Output: ROM Status Code: 0x000000F3 Description:
DSP_0: GEL Output: Error code not recognized
DSP_0: GEL Output: Program Counter (PC) = 0x0000040C
DSP_0: GEL Output:
DSP_0: GEL Output: ---------------------------------------------
DSP_0: GEL Output: | Clock Information |
DSP_0: GEL Output: ---------------------------------------------
DSP_0: GEL Output:
DSP_0: GEL Output: PLLs configured to utilize crystal.
DSP_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
DSP_0: GEL Output:
DSP_0: GEL Output: NOTE: All clock frequencies in following PLL sections are based
DSP_0: GEL Output: off OSCIN = 1103403942 MHz. If that value does not match your hardware
DSP_0: GEL Output: you should change the #define in the top of the gel file, save it,
DSP_0: GEL Output: and then reload.
DSP_0: GEL Output:
DSP_0: GEL Output: ---------------------------------------------
DSP_0: GEL Output: | PLL0 Information |
DSP_0: GEL Output: ---------------------------------------------
DSP_0: GEL Output:
DSP_0: GEL Output: PLL0_SYSCLK1 = 1 MHz
DSP_0: GEL Output: PLL0_SYSCLK2 = 24 MHz
DSP_0: GEL Output: PLL0_SYSCLK3 = 12 MHz
DSP_0: GEL Output: PLL0_SYSCLK4 = 3 MHz
DSP_0: GEL Output: PLL0_SYSCLK5 = 6 MHz
DSP_0: GEL Output: PLL0_SYSCLK6 = 24 MHz
DSP_0: GEL Output: PLL0_SYSCLK7 = 24 MHz
DSP_0: GEL Output: Error: PLL0_SYSCLK2 must equal PLL0_SYSCLK1 / 2
DSP_0: GEL Output: Error: PLL0_SYSCLK4 must equal PLL0_SYSCLK1 / 4
DSP_0: GEL Output: Error: PLL0_SYSCLK6 must equal PLL0_SYSCLK1 / 1
DSP_0: GEL Output:
DSP_0: GEL Output: ---------------------------------------------
DSP_0: GEL Output: | PLL1 Information |
DSP_0: GEL Output: ---------------------------------------------
DSP_0: GEL Output:
DSP_0: GEL Output: PLL1_SYSCLK1 = 24 MHz
DSP_0: GEL Output: PLL1_SYSCLK2 = 24 MHz
DSP_0: GEL Output: PLL1_SYSCLK3 = 24 MHz
DSP_0: GEL Output:
DSP_0: GEL Output: ---------------------------------------------
DSP_0: GEL Output: | PSC0 Information |
DSP_0: GEL Output: ---------------------------------------------
DSP_0: GEL Output:
DSP_0: GEL Output: State Decoder:
DSP_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
DSP_0: GEL Output: 1 = SyncReset (reset assered, clock on)
DSP_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
DSP_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
DSP_0: GEL Output: >3 = Transition in progress
DSP_0: GEL Output:
DSP_0: GEL Output: Module 0: EDMA3CC (0) STATE = 43
DSP_0: GEL Output: Module 1: EDMA3 TC0 STATE = 0
DSP_0: GEL Output: Module 2: EDMA3 TC1 STATE = 0
DSP_0: GEL Output: Module 3: EMIFA (BR7) STATE = 0
DSP_0: GEL Output: Module 4: SPI 0 STATE = 0
DSP_0: GEL Output: Module 5: MMC/SD 0 STATE = 3
DSP_0: GEL Output: Module 6: AINTC STATE = 0
DSP_0: GEL Output: Module 7: ARM RAM/ROM STATE = 3
DSP_0: GEL Output: Module 9: UART 0 STATE = 3
DSP_0: GEL Output: Module 10: SCR 0 (BR0/1/2/8) STATE = 0
DSP_0: GEL Output: Module 11: SCR 1 (BR4) STATE = 3
DSP_0: GEL Output: Module 12: SCR 2 (BR3/5/6) STATE = 3
DSP_0: GEL Output: Module 13: PRUSS STATE = 3
DSP_0: GEL Output: Module 14: ARM STATE = 0
DSP_0: GEL Output: Module 15: DSP STATE = 0
DSP_0: GEL Output:
DSP_0: GEL Output: ---------------------------------------------
DSP_0: GEL Output: | PSC1 Information |
DSP_0: GEL Output: ---------------------------------------------
DSP_0: GEL Output:
DSP_0: GEL Output: State Decoder:
DSP_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
DSP_0: GEL Output: 1 = SyncReset (reset assered, clock on)
DSP_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
DSP_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
DSP_0: GEL Output: >3 = Transition in progress
DSP_0: GEL Output:
DSP_0: GEL Output: Module 0: EDMA3CC (1) STATE = 3
DSP_0: GEL Output: Module 1: USB0 (2.0) STATE = 0
DSP_0: GEL Output: Module 2: USB1 (1.1) STATE = 0
DSP_0: GEL Output: Module 3: GPIO STATE = 0
DSP_0: GEL Output: Module 4: UHPI STATE = 0
DSP_0: GEL Output: Module 5: EMAC STATE = 0
DSP_0: GEL Output: Module 6: DDR2 and SCR F3 STATE = 0
DSP_0: GEL Output: Module 7: MCASP0 + FIFO STATE = 0
DSP_0: GEL Output: Module 8: SATA STATE = 0
DSP_0: GEL Output: Module 9: VPIF STATE = 0
DSP_0: GEL Output: Module 10: SPI 1 STATE = 0
DSP_0: GEL Output: Module 11: I2C 1 STATE = 0
DSP_0: GEL Output: Module 12: UART 1 STATE = 0
DSP_0: GEL Output: Module 13: UART 2 STATE = 0
DSP_0: GEL Output: Module 14: MCBSP0 + FIFO STATE = 0
DSP_0: GEL Output: Module 15: MCBSP1 + FIFO STATE = 0
DSP_0: GEL Output: Module 16: LCDC STATE = 0
DSP_0: GEL Output: Module 17: eHRPWM (all) STATE = 0
DSP_0: GEL Output: Module 18: MMC/SD 1 STATE = 0
DSP_0: GEL Output: Module 19: UPP STATE = 0
DSP_0: GEL Output: Module 20: eCAP (all) STATE = 0
DSP_0: GEL Output: Module 21: EDMA3 TC2 STATE = 0
DSP_0: GEL Output: Module 24: SCR-F0 Br-F0 STATE = 0
DSP_0: GEL Output: Module 25: SCR-F1 Br-F1 STATE = 3
DSP_0: GEL Output: Module 26: SCR-F2 Br-F2 STATE = 3
DSP_0: GEL Output: Module 27: SCR-F6 Br-F3 STATE = 3
DSP_0: GEL Output: Module 28: SCR-F7 Br-F4 STATE = 0
DSP_0: GEL Output: Module 29: SCR-F8 Br-F5 STATE = 0
DSP_0: GEL Output: Module 30: Br-F7 (DDR Contr) STATE = 0
DSP_0: GEL Output: Module 31: L3 RAM, SCR-F4, Br-F6 STATE = 0
====
I believe we had inserted enough delay on uC code, but we have still the problem.
And now I'm wondering if we might have something issues in HW because the above message
indicates unknown error during boot sequence.
Could you please let me know
- What is this error ?
- Any suggestions to fix this issue
