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Display resolution

ranchu
Guru 20755 points

Hello,

I would like to understand if there is any hardware constraints on display resolution.
I first understood that there are none, but I see in vpshal_hdvenc.c that there is use of some index of resolution as input bits to some register. I would like to ask:
1. Is there some constrains by hardware for only these specific resolutions in DVO2 or we can use as output any resolution, frame-rate ? I didn't find such constrain in technical documnets, or register used in the above command.
2. Is there a similiar hardware constrain for the input for capturing or we can use as input any resolution, frame-rate (as long as it's under 165 HZ) ? Thank you! Ran VPSHAL_HDVENC_MODE_480I60 = 0,

VPSHAL_HDVENC_MODE_480P60,
VPSHAL_HDVENC_MODE_1080I60,
VPSHAL_HDVENC_MODE_720P60,
VPSHAL_HDVENC_MODE_576i60,
VPSHAL_HDVENC_MODE_576P60,
VPSHAL_HDVENC_MODE_1080P60,
VPSHAL_HDVENC_MODE_MANUAL,

regsOvly->CFG0 |= ((dispMode << CSL_VPS_HD_VENC_A_CFG0_DM_SEL_SHIFT) & CSL_VPS_HD_VENC_A_CFG0_DM_SEL_MASK);

  • 0
    TI__Mastermind 20245 points

    Hi,

    These enums are added for easy configuration of mostly used modes. But Encoder can support any resolution upto 165MHz. Further same is true for capture as long as it meets BT656, BT601 or BT1120 standard upto 165MHz clock.

  • 0 in reply to HardikShah
    Guru 20755 points

    Hi Hardik,

    Thank you for the answer.
    Regarding the Display resolution, as I posted in the previous message, in vps/hal/src/vpshal_hdvenc.c there is setting of CFG0 register using dispMode . What is this register ? I suppose each value of  dispMode bits in this register, is defined by different hardware behaviour, so my question is if there is any hardware limitation on resolution for hdvenc.

    Best Regards,

    Ran

            /* Set the Video Mode in the register */
            regsOvly->CFG0 &= ~CSL_VPS_HD_VENC_A_CFG0_DM_SEL_MASK;
            regsOvly->CFG0 |= ((dispMode <<
                    CSL_VPS_HD_VENC_A_CFG0_DM_SEL_SHIFT) &
                        CSL_VPS_HD_VENC_A_CFG0_DM_SEL_MASK);

  • 0 in reply to ranchu
    TI__Guru**** 477195 points

    Hi,

     

    This is not used for the DVO outputs, so need not have to worry.

     

    Thx,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Guru 20755 points

    Hi Brijesh,

    Thank you vey much for the reply. 
    Is it HDMI output that this register is setting ? Is the HDMI output limited to specific resolutions as written in hdvenc? It is important for me to understand since if I need to add new input or output resolution , I need to understand  what list of changes should be made.  
    If this register only relevant for HDMI, it is also in my concern, since I will anyway first check the new resolution with DVR EVM. Besides this register, there is a list of different resolutions in ti\psp\vps\fvid2.h. I wander if I should add the new required resolution into this list in order to support new resolution in input or output. If there are any guidelines as to the list of code changes for supporting new input or output resolution, it will be helpful.

    Thanks,

    Ran


  • 0 in reply to ranchu
    TI__Guru**** 477195 points

    Hi Ran,

     

    This is not even for HDMI, it is for HDDAC output.

     

    Thx,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Guru 20755 points

    Hi Brijesh,

    I hope you can please answer one more thing in the same context:

    Hardik mentioned limitation of input resolution of BT656, BT601 or BT1120. I would like to understand if it is some hardware limitation or driver limitation.
    We are required to capture 512x512 30fps resolution and I'm  afraid that this resolution is not part of these standards. I would like to know if it is possible to add support for this resolution in framework/firmaware, and if yes, if you can give me some points as to how it should be done.

    Many Thanks!!

    Ran

  • 0 in reply to ranchu
    TI__Guru**** 477195 points

    Hi Ran,

     

    What Hardik mentioned is about the signaling, you could have bt656 or bt1120 style of embedde sync or bt601 style of discrete sync input. It does not mean it can support only few resolutions. You could have 512x512@30fps resolutions as an input in either embedded sync or discrete sync format.

     

    Thanks,

    Brijesh Jadav

  • 0 in reply to Brijesh Jadav
    Guru 20755 points

    Hi Brijesh,

    Analog output resolution is limited to only the specified resolutions, as I understand from your post. Is HDMI resolutions also limited ?

    Thanks,

    Ran

  • 0 in reply to ranchu
    TI__Mastermind 20245 points

    Hi,

    Both analog and digital output can support variety of resolutions. What specific resolution. which specific resolution you are looking for?

  • 0 in reply to HardikShah
    Guru 20755 points

    Hi Hardik,

    according to spec DVO formats can support any resolution up to 165Mhz, But as to HD analog I see that only a small set of resolutions is allowed (3 bits register is controlling which resolution is set in the HDDAC). Now I would like to ask what about HDMI ? according to datasheet figure of HDVPSS it seems that both HDMI and DVO2 are tied together as output from the same HDVENC HW. Does it mean that HDMI HW can show any resolution (as long as it is up to 165MHZ) or is there any limitation on HDMI output ?

    Thanks,

    Ran