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Watchdog Timer keeps going up when Stopped in Emulator

Erick Higa
Intellectual 860 points

I'm using the 6670 (rev 2.0), and setup Timer0 to work as a watchdog timer for core 0.  It works fine however even with the SOFT and FREE bits in EMUMGT_CLKSPD set to 0, the clock continues to count up.  This makes it a bit difficult to debug things once it is initialized.  Is there anything I am missing that I need to do to not get it to count up when the emulator his a break point?

  • 0
    TI__Mastermind 30825 points

    Erick,

    I'm having someone confirm this, but I believe that the WD Timer cannot be halted by the Emulation.  I believe Emulation normally halts the Timers by setting the 'Gate Internal Clock' pin on the MUX to prevent internal clock from feeding to the Timer when Emulation is halted.  If that is correct, then since the WD Timer mode does not support the gate internal clock (see section 4.2 of C66x Timer UG SPRUGV5) then you would not be able to halt the WD Timer during emulation.

    I'd suggest setting the WD Timer value very high for the time being, while trying to debug none WD Timer Timeout related issues, and set it back when trying to test things to insure you're not getting WD Timeouts.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    TI__Mastermind 30825 points

    Erick,

    I checked with our design team and my statement above was incorrect about this.  The WD Timer (actually 64 bit timer used in any mode for that matter) will only halt when all the cores are halted.  So, you'll need to make sure all the cores are halted to stop the WD Timer.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Intellectual 860 points

    Yupp that was it, thanks Chad, I was bypassing the other cores in the JTAG chain so they weren't getting haulted.

    Thanks for the info