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ARDY gets low between data transfer

ehsan betoche
Prodigy 10 points

hi,

I work on fpga controller for connect 3 C6000 dsp so that they work together parallel.

would you help me and answer my question?

in TI documents shows that ardy must get low while strobe is comming. if i make ardy low between data transfer and after strobe, what will happen?

does it work?

if it doesn't work what should i do?

i want to stop writing before fifo get full. 

thanks.

  • 0
    TI__Guru* 84110 points

    Ehsan,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages. Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics.

    It may help to know which specific C6000-family DSP you are using.

    Please specify the documentation detail about ARDY "must get low". This may not be a requirement, but that may not be what you are asking. Please explain your question more.

    If what you want to do is to hold ARDY low until the FPGA is ready to accept data, different DSPs handle this in different ways. In general, yes you can do this.

    Another method is to use a GPIO from the FPGA that pulses whenever it is ready to receive data. But this may not help depending on the nature of your data flow. I cannot make other suggestions without more information on what you are trying to achieve with this design.

    Regards,
    RandyP