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Evaluating PRU - Some questions

B. R.
Prodigy 145 points
Other Parts Discussed in Thread: AM3359, SYSBIOS

Hello guys,

I'm trying to evaluate the possibilities of the PRU-ICSP on AM3359, but I am very new to this topic and also in general with such high integrated ARM devices and hope you can help to answer me a few questions...


1.     Signal identifier pr1_
Some signals related to the PRU are named pr1_. What does this stand for?


2.     MII_RT
Except inside PRU reference guide I couldn't find the term MII_RT in any other document. What is the expression of RT? Realtime? This is not a part of the Ethernet Subsystem, right?


3.      Pinmuxing: mii0_rxd[3:0]
PRU_ReferenceGuide, page 20: Figure 3. PRU-ICSS Internal Signal Muxing: pin_mux_sel[0]
Where else can I find the intern signals mii0_rxd[3:0] in any technical document related to am335x?
I searched inside TRM (SPRUH73F), PRU_Refguide (SPRUHF8) and in the AM3359 summary (SPRS717D), but was not able to find any further use of these signals.
So what is the use/advantage of this pin muxing configuration? And how do I access/manipulate them?


4.      Ethernet ports index
See Figure 2. PRU-ICSS Integration on page 15.
Is it correct that pr1_mii0_ is connected to ethernet port 1 and pr1_mii1_ to ethernet port 2? So the internal port 0 can not be used by the PRU?


Thank you for your help.

Greetings

  • 0
    TI__Intellectual 1835 points

    1. This is just the way the signals got named. Part of the reason is TI internal design database legacy. So, there is no particular meaning or interpretation of this prefix that is relevant for AM335x line of products.

    2. MII_RT is the real-time MII interface module inside PRU-ICSS. This is used for industrial communications such as EtherCAT. This is part of PRU-ICSS but has no relation to the Ethernet subsystem that is used for 10/100/1000 Mbps switching.PRU-ICSS is an independent module and MII_RT is a part of that. TI has chosen to not open it up for customer uses beyond what is supported by the SYS/BIOS based industrial SDK.

    3. The advantage of this internal pin-multiplex is to enable more applications which would not be possible if the MII0 RXD bus was only available on one set of pins. As mentioned in #2, this is used only by TI internal teams and released in SYSBIOS industrial SDK. So, at present, there is no support for programming MII interface via PRUs.

    4. The pr1_mii0/1 are two Ethernet ports independent of the gigabit switch ports. There are internal connections in the device where PRUs can also send/receive data from memory and receive/send to pr1_mii0/1 ports.

    Thanks.

    Maneesh

  • 0 in reply to Maneesh
    Prodigy 145 points

    Thank you so far Manessh!

    Maneesh said:
    4. The pr1_mii0/1 are two Ethernet ports independent of the gigabit switch ports. There are internal connections in the device where PRUs can also send/receive data from memory and receive/send to pr1_mii0/1 ports.

    Can you go more in detail on this statement, please?

    4.1. Do I understand it correct, that I cannot access these signals showed in Fig. 2 connected to the MII_RT module, because no support for programming MII_RT is offered at the moment?

    pr1_mii_*
    pr1_mii0_*
    pr1_mdio_*
    pr1_mii1_*

    4.2. So this means if I want to use PRU for ethernet communication I have to use other (physical) pins which I can only access through following registers?

    pr1_pru0_r31[16:0]
    pr1_pru0_r30[15:0]
    pr1_pru1_r31[16:0]
    pr1_pru1_r30[15:0]

    4.3. Is it also possible to access/change the GPIOs by read/write the specified GPIO memory address direct via constant table?

  • 0 in reply to B. R.
    TI__Intellectual 1835 points

    4.1 Yes. Your interpretation is correct. All pr1_mii_* are unsupported for custom applications as of now. 

    4.2 I would not advise using the R30/R31 for Ethernet as it is unlikely to work in an efficient manner. As you can guess the reason, TI would not create MII_RT module if it were efficient to do MII communication with R30/31 alone. The switching on MII interface is 25 MHz... that is just 8 cycles of PRU. It will probably be barely enough to communicate to a PHY. And note, the clock for TX and RX is not aligned with PRU internal clock on which R30/R31 bits will switch. 

    4.3 Yes. PRU can access a lot of peripherals in AM335x.

    Thanks,

    Maneesh