Hi,
I have written uPP device driver in linux for Am1808 and I am using it in Transmit mode with FPGA (Chipscope) on otherside, in following set configurations:
UPCTL.DPF = Right justified, Zero Extended
UPCTL.DPW = No data packing
UPCTL.IW = 8 bit Interface
UPCTL.DR = Single data rate
UPCTL.DDRDEMUX = Disabled
UPCTL.SDRTXIL = Disabled
UPCTL.CHN = Dual Channel Mode
UPCTL.MODE = All Transmit
UPTCR.TXSIZE = 64 Bytes
UPTCR.RDSIZE = 64 Bytes
UPIVR.VAL = 255
UPQD0 = ADDRESS
UPQD1.LNCNT = 1
UPQD1.BCNTH = 0
UPQD1.BCNT = 0
UPQD2.LNOFFSETTH = 0
UPQD2.LNOFFSET = 0
UPICR.TRISB = 0
UPICR.WAITB = 1
UPICR.TRISA = 0
UPICR.WAITA = 1
When DMA registers are configured, the data recieved just after the "Enable" and "Start" signals are asserted has some "Channel Idle Values " as set in (UPIVR).
For example: if Idle state value is set to 255 in UPIVR register and 64 bytes ranging from 0 to 64 are transfered; Data is recieved in following pattern:
Byte 0: 255
Byte 1: 255
Byte 2: 255
Byte 3: 255
Byte 4: 255
Byte 5: 255
Byte 6: 255
Byte 7: 255
Byte 8: 255
Byte 9: 255
Byte 10: 255
Byte 11: 255
Byte 12: 255
Byte 13: 255
Byte 14: 255
Byte 15: 255
Byte 16: 255
Byte 17: 255
Byte 18: 255
Byte 19: 255
Byte 20: 255
Byte 21: 255
Byte 22: 255
Byte 23: 255
Byte 24: 0
Byte 25: 1
Byte 26: 2
Byte 27: 3
Byte 28: 4
Byte 29: 5
Byte 30: 6
Byte 31: 7
Byte 32: 8
Byte 33: 9
Byte 34: 10
Byte 35: 11
Byte 36: 12
Byte 37: 13
.
.
.
.
.
Byte 60: 37
Byte 61: 38
Byte 62: 39
Byte 63: 40
The count for which these Idle values are recieved varies and is not constant.The same behaviour is observed when used in Digital Loop Back (DLB) from Channel A to B.
Please direct me on this Issue,
Thanks
regards
usama