C6678 DDR3 Initialization fails

Hi all,

we have a problem with DDR3 operation on a self designed C6678 board.
We use the same DDR3 architecture as on the EVM6678 but with
Nanya NT5CB128M16BP-CGI memory component (see http://www.nanya.com/NanyaAdmin/GetFiles.ashx?ID=961).
So we have DDR3-1333/64Bit without ECC.

We started with the EVM GEL file and adjusted the timing values for 666.667MHz
according to the Nanya data sheet. For the leveling values, we took the trace lengths
from our PCB design tool and used the register settings from the spread sheet
DDR3_PHY_Calc_V8. Our PCB tool reports for 153ps/inch delay, so we used this value
instead of the delay from the approximation formula given in the instructions.

Not sure if this is important, but the spread sheet reports the values for
DATAx_WRLVL_INIT_RATIO *all* zero. Is this a problem?

However, the initialization never succeeds. The bits (6:4) in the DDR3
controller status register (0x21000004) are all 1, so the leveling seems to fail
completely. I tried to acces the address range after 0x80000000 with Code Composer's
memory browser. Write operations are completely effectless and read
operations result in a random pattern (but with most data words 0).

I did not check the details, but I could not find a violation of the design rules
so far. The DDR3 clock is present and has a jitter below +/- 125ps. I measured only
one lane of the differential DDR3 clock, so I expect that the jitter is even lower
when analyzing the differential signal. The DDR3 voltage is slighly too high (1.56V).

Here is the ddr3_setup_auto_lvl_1333() funtion from the GEL with our modifications:



dr3_setup_auto_lvl_1333()
{
      
    int i,TEMP,startlo, stoplo,starthi, stophi;
    float DDR3_FREQ, DDR3_CYCLE;
        
    KICK0 = KICK0_UNLOCK;
    KICK1 = KICK1_UNLOCK;

    /* Wait for PLL to lock = min 500 ref clock cycles.
       With refclk = 100MHz, = 5000 ns = 5us */
    Delay_milli_seconds(1);

    /***************** 3.2 DDR3 PLL Configuration ************/
    /* Done before, M=19, D=0 */

    /**************** 3.0 Leveling Register Configuration ********************/
    /* Using partial automatic leveling due to errata */

    /**************** 3.3 Leveling register configuration ********************/
    DDR3_CONFIG_REG_0 &= ~(0x007FE000);  // clear ctrl_slave_ratio field
    DDR3_CONFIG_REG_0 |= 0x00200000;     // set ctrl_slave_ratio to 0x100
    DDR3_CONFIG_REG_12 |= 0x08000000;    // Set invert_clkout = 1
    DDR3_CONFIG_REG_0 |= 0xF;            // set dll_lock_diff to 15

    //From 4.2.1 Executing Partial Automatic Leveling -- Start
    DDR3_CONFIG_REG_23 |= 0x00000200;    //Set bit 9 = 1 to use forced ratio leveling for read DQS
    DDR3_CONFIG_REG_23 &= 0xffffff00;   
    DDR3_CONFIG_REG_23 |= 0x00000013;
    GEL_TextOut("DDR3: read DQS ratio = 0x13h.\n");  
    
    
        //From 4.2.1 Executing Partial Automatic Leveling -- End

    //Values with invertclkout = 1
    /**************** 3.3 Partial Automatic Leveling ********************/
    
    /* Note: all values from from DDR3_PHY_Calc_V8.xls */
   
    DATA0_WRLVL_INIT_RATIO = 0x00;
    DATA1_WRLVL_INIT_RATIO = 0x00;
    DATA2_WRLVL_INIT_RATIO = 0x00;
    DATA3_WRLVL_INIT_RATIO = 0x00;
    DATA4_WRLVL_INIT_RATIO = 0x00;
    DATA5_WRLVL_INIT_RATIO = 0x00;
    DATA6_WRLVL_INIT_RATIO = 0x00;
    DATA7_WRLVL_INIT_RATIO = 0x00;
    DATA8_WRLVL_INIT_RATIO = 0x00;


    DATA0_GTLVL_INIT_RATIO = 0xBA;
    DATA1_GTLVL_INIT_RATIO = 0xB8;
    DATA2_GTLVL_INIT_RATIO = 0xA0;
    DATA3_GTLVL_INIT_RATIO = 0xA0;
    DATA4_GTLVL_INIT_RATIO = 0x7C;
    DATA5_GTLVL_INIT_RATIO = 0x7E;
    DATA6_GTLVL_INIT_RATIO = 0x5D;
    DATA7_GTLVL_INIT_RATIO = 0x5C;
    DATA8_GTLVL_INIT_RATIO = 0x00;

    //Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0
    DDR_DDRPHYC &= ~(0x00008000);
    DDR_DDRPHYC |= (0x00008000);
    DDR_DDRPHYC &= ~(0x00008000);

    /***************** 3.4 Basic Controller and DRAM Configuration ************/
    DDR_SDRFC    = 0x00005162;    // enable configuration

    DDR3_FREQ = 666.666666e+06;
    DDR3_CYCLE = 1.0/DDR3_FREQ;
   

    TEMP = 0;
    TEMP |= TimeToField(13.125e-09,     DDR3_FREQ, 25);   // T_RP
    TEMP |= TimeToField(13.125e-09,     DDR3_FREQ, 21);   // T_RCD  
    TEMP |= TimeToField(15.0e-09,       DDR3_FREQ, 17);   // T_WR
    TEMP |= TimeToField(36.0e-09,       DDR3_FREQ, 12);   // T_RAS
    TEMP |= TimeToField(49.5e-09,       DDR3_FREQ, 6);    // T_RC
    TEMP |= TimeToField(30.0e-09/4.0,   DDR3_FREQ, 3);    // T_RRD = T_FAW/4
    TEMP |= TimeToField(7.5e-09,        DDR3_FREQ, 0);    // T_WTR = max(7.5ns, 4*T_CK)
    GEL_TextOut("\DDR3 SDTIM1=%xh\n",,8,,,TEMP);   
    DDR_SDTIM1 = TEMP;
 

    TEMP = 0;
    TEMP |= ClckToField(3, 28);                       // T_XP = max(3 clock cycles, 7.5ns)
    TEMP |= TimeToField(170.0e-09, DDR3_FREQ, 16);    // T_XSNR = 160ns+10ns
    TEMP |= ClckToField(512, 6);                      // T_XSRD
    TEMP |= TimeToField(7.5e-09,   DDR3_FREQ, 3);     // T_TRP = max(4 clock cycles, 7.5ns)
    TEMP |= TimeToField(6.0e-09,   DDR3_FREQ, 0);     // T_CKE = max(3 clock cycles, 6ns)
    GEL_TextOut("DDR3 SDTIM2=%xh\n",,8,,,TEMP);
    DDR_SDTIM2 = TEMP;

    TEMP = 0;   
    TEMP |= 0x5 << 28;                               // T_PDLL_UL (fixed value)
    TEMP |= 0x5 << 24;                               // T_CSTA bit (fixed value)   
    TEMP |= ClckToField(4, 21);                      // T_CKESR = 3 clocks + 1 clock
    TEMP |= ClckToField(64, 15);                     // ZQ_ZQCS
    TEMP |= TimeToField(160.0e-3, DDR3_FREQ, 4);     // T_RFC
    TEMP |= 0xF;                                     // T_RAS_MAX (fixed value)
    GEL_TextOut("DDR3 SDTIM3=%xh\n",,8,,,TEMP);
    DDR_SDTIM3 = TEMP;  
 


    DDR_DDRPHYC  = 0x0010010F;           

    DDR_ZQCFG    = 0x70073214;

    DDR_PMCTL    = 0x0;

    DDR_SDRFC = 0x00005162; // enable configuration

    /* DDR_SDCFG    = 0x63062A32; */
    /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 //0x63222A32;    // last config write DRAM init occurs */
    TEMP = 0;
    TEMP |= 0x3 << 29; // SDRAM_TYPE bit field 31:29 (fixed value)
    TEMP |= 0x0 << 27; // IBANK_POS bit field 28:27
    TEMP |= 0x3 << 24; // DDR_TERM bit field 26:24
    TEMP |= 0x0 << 21; // DYN_ODT bit field 22:21
    TEMP |= 0x1 << 18; // SDRAM_DRIVE bit field 19:18
    TEMP |= 0x2 << 16; // CWL bit field 17:16
    TEMP |= 0x0 << 14; // NM bit field 15:14
    TEMP |= 0xA << 10; // CL bit field 13:10
    TEMP |= 0x4 << 7; // ROWSIZE bit field 9:7
    TEMP |= 0x3 << 4; // IBANK bit field 6:4
    TEMP |= 0x0 << 3; // EBANK bit field 3:3
    TEMP |= 0x2; // PAGESIZE bit field 2:0
    DDR_SDCFG = TEMP;

    //Wait 600us for HW init to complete
    Delay_milli_seconds(1);

    DDR_SDRFC = 0x0000144A;       //Refresh rate = (7.8*666MHz)

    /**************** 4.2.1 Executing Partial Automatic Leveling ********************/

    DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling

    DDR_RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value  

    //(0x34) instead
    //Wait for min 1048576 DDR clock cycles for leveling to complete = 1048576 * 1.5ns = 1572864ns = 1.57ms.
    //Actual time = ~10-15 ms
    Delay_milli_seconds(1);
    GEL_TextOut("\nDDR3 initialization is complete.\n");
}


I have no idea what's going wrong here.
Can you give me a starting point for searching the cause of the problem?



Thank you very much.

Marcus Bednara