Hi,
In our C6655 based custom design, there is no load on 1.5V rails except PCIe bus interface. There are no external memory, SGMII, Hyperlink and SRIO interfaces.
Though ,there is very light load on 1.5V rails , should 1.5V rail be designed /capable to deliver at max current rate as stated in datasheet?
Is it possible to design 1.5V at 100mA ( 60mA for PCIe and 40mA safe over margin) size?
Thanks in advance for your reply.
Regards,
Udaya