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AM335X ZCE Layout

JasonHaedt
Genius 3320 points

Dear TI,

I am implementing an AM335x ZCE layout and was going through all the DRC errors when doing via-channel. One item I do not see specified in the following wiki: http://processors.wiki.ti.com/index.php/General_hardware_design/BGA_PCB_design is what to do with soldermask clearance DRC constraints.  For these type of 0.65mm pitch designs, what is the recommended soldermask expansion?

-Jason

  • 0
    TI__Intellectual 2150 points

    Depending on your specific PCB constraints accounting for trace widths, pad sizes, and spacing requirements, you could go with up to + 0.004 on the solder mask on the ZCE package.  You should verify your particular board details though with your PCB fabricator to make sure you do not have manufacturing issues.