C6678 UART FIFO-interrupt mode problem

xiang_li

Hi all,

Recently,I have developed a uart driver base on pdk_C6678_1_0_0_17\packages\ti\platform\evmc6678l\platform_lib.But I still feeling confused about FIFO-interrupt mode.

I config uart in FIFO-interrupt mode,set receiver FIFO trigger level at 8 byte.(system interrupt #148)

Q1:How to read from FIFO and How to read many character every time. FIFO`s first address and RBR`s first address is same?

(Now,I read data from RBR or FIFO by CSL_FEXT(hUartRegs->RBR, UART_RBR_DATA);

And I guess they have same first address)

Q2:In testing,It seems like in no-FIFO mode as User Guide- When a character is placed in RBR,an interrupt is generated.

( I have enable FIFO by CSL_FINS (hUartRegs->FCR, UART_FCR_FIFOEN, CSL_UART_FCR_FIFOEN_ENABLE);

I think it should that an interrupt is generated when i received 8 byte data from PC every time.

Q3:As User Guide said,In FIFO mode,the interrupt is generated when the FIFO is filled to the trigger level,and it is cleared when the

FIFO contents drop below the trigger level.

The situation that I have received 8 byte data from PC in FIFO,generate an interrupt,then I read data from FIFO in interrupt routine.

The problem that If I read a character from FIFO, I feel it is not different from non-FIFO, so I must read many characters everytime?

Thanks,

over 13 years ago

0 Steven Ji over 13 years ago

TI__Genius 12065 points

Li,

1. You will still read from RBR in FIFO mode.

The RBR, receiver buffer register contains the byte received if no FIFO is used, or the oldest unread byte with FIFO's. If FIFO buffering is used, each new read action of the register will return the next byte, until no more bytes are present. Bit 0 in the LSR line status register can be used to check if all received bytes have been read. This bit wil change to zero if no more bytes are present.

2. You are probably receiving the "Receiver Time-out" interrupt.

If you setup the FIFO trigger level correctly (enable FIFOEN bit first and then setup RXFIFTL field, as mentioned in UART user guide section 3.5) but still seem to enter into the ISR for every character received, please check the IIR register to see if the INTID field indicating that the "Receiver time-out" has been received.

In FIFO mode, if there are no characters have been removed from or input to the receiver FIFO during the last four character times, and there is at least one character in the receiver FIFO during this time, the time-out interrupt will be generated. And it is sharing the same interrupt line of "receiver data-ready" interrupt and is very likely to happen if you press the keyboard in the PC as the input to UART.

3. The advantage of FIFO mode is that you do not need to generate interrupt for every single character transfer and you can generate the DMA event to EDMA and trigger the receive/transmit transfer automatically.

Please take a look at the section 2.9 "DMA event support" and section 3.5 "FCR" in UART user guide for details.

0 xiang_li over 13 years ago in reply to Steven Ji

Intellectual 935 points

Hi,Steven

Thank you reply me so detail.

Your answer is helpful.

I have finished the mission,and learn more something.

Thanks,

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C6678 UART FIFO-interrupt mode problem