Hi.
I'm trying to get a grip on programming the descriptor registers for the DMA channels for the UPP. I'm following the "step by step" procedures in section 2.6.1 of SPRUGJ5B.
This is a Linux device driver, and everything seems to be going well (I think!). After writing data to the UPP in DLB mode, I can see the interrupts being fired [EOLI, EOWI, EOLQ, EOWQ, etc,], and I am not seeing errors [DPEx, UORx, ERRx, etc]).
However, I cannot get the descriptor registers right. Here's my understanding ( where, for my purposes, Channel A->XMIT, Channel B->RECV):
- Program UPID0 with the base address of a 16384 byte buffer.
- Program UPID1 with a LNCNT == 4, BCNTH == 4096
- Program UPID2 with LNOFFSETH == BCNTH == 4096.
- Program UPQD0 with the base address of another 16384 byte buffer
- Program UPQD1 with LNCNT == 4, BCNTH == 4096
- Program UPQD2 with LNOFFSETH == BCNTH == 4096.
Subsequently, in my Linux "userspace" test application, I can see my userspace data being written to the xmit buffer, and I see both the EOLI and EOLW interrupts in my ISR. I print out the DMA channel status registers (UPxS0, UPxS1, UPxS2) from within the ISR, and I see no changes.
If it helps, I've attached my device driver source code. My intentions are to release a (working!) version of this via GPL license.
Thanks!
