PLL Clock trouble

Junji Takahata

Prodigy 40 points

Device : TMS320C5535AZHH10

Environment : CCS V4 + XDS100v2

Behavior : as below

After booting up, set registers related with PLL as 100MHz clock speed.

Change clock mode from "BYPASS MODE" to "PLL MODE".

Then jump to reset vector address and hung up.

Clock source is 32.768KHz crystal.

Emulator works well under "BYPASS MODE".

What possibility cause this reset exception ?

over 13 years ago

0 Junji Takahata over 13 years ago

Prodigy 40 points

Supplement

setting programs are ...

PLL_config (hPll, pConfigInfo) in systemInit(void)

void systemInit(void)
{
    Uint16 i;
    PLL_Obj pllObj;
    CSL_Status status;
    PLL_Handle hPll;
    PLL_Config *pConfigInfo;
    PLL_Config pllCfg_v2_100MHz    = {0x8BE8, 0x8000, 0x0806, 0x0000};
//    PLL_Config pllCfg_v2_100MHz    = {0x85f4, 0x8000, 0x0806, 0x0000};

    /* Config Idle control */
    SYS_ICR = 0xFF2E;
    asm(" IDLE");

    /* Reset peripherals */
    CSL_FINS(CSL_SYSCTRL_REGS->PSRCR, SYS_PSRCR_COUNT, 0x02);
    CSL_SYSCTRL_REGS->PRCR = 0xfb;

    /* Delay for devices to reset */
    for (i=0; i< 200; i++);

    /* Setup PLL */
    status = PLL_init(&pllObj, CSL_PLL_INST_0);
    hPll = (PLL_Handle)(&pllObj);
    PLL_reset(hPll);
    pConfigInfo = &pllCfg_v2_100MHz;

    status = PLL_config (hPll, pConfigInfo);

Hung up here.

I executed inside PLL_config step by step.

Thanks

0 Juliana Mansell over 13 years ago in reply to Junji Takahata

TI__Intellectual 1755 points

Hi,

Can you substitute the code for your PLL_config for this and see if it works:

CSL_Status PLL_config(PLL_Handle hPll,
PLL_Config *pconfigInfo)
{
Uint16 timeout = TIMEOUT;
CSL_Status status = CSL_SOK;
Uint16 x = 0;
if(NULL == hPll)
{
status = CSL_ESYS_BADHANDLE;
return status;
}

if(NULL == pconfigInfo)
{
status = CSL_ESYS_INVPARAMS;
return status;
}

hPll->pllConfig = pconfigInfo;

/* Force to BYPASS mode */
CSL_FINST(hPll->sysAddr->CCR2, SYS_CCR2_SYSCLKSEL, BYPASS);

/* Set RSVD = 0 in CGCR1 */
CSL_FINST(hPll->sysAddr->CGCR1, SYS_CGCR1_RSVD, CLEAR);
/*Program RDRATIO, M, and RDBYPASS in CGCR1 and CGCR2*/
hPll->sysAddr->CGCR2 = pconfigInfo->PLLINCNTL;
CSL_FINS(hPll->sysAddr->CGCR1, SYS_CGCR1_M,(pconfigInfo->PLLCNTL1 & CSL_SYS_CGCR1_M_MASK));
/*Program ODRATIO and OUTDIVEN in CGCR4*/
hPll->sysAddr->CGCR4 = pconfigInfo->PLLOUTCNTL;
/*Write 0806g to CGCR3*/
hPll->sysAddr->CGCR3 = pconfigInfo->PLLCNTL2;
/*Set PLL_PWRDN = 0*/
CSL_FINS(hPll->sysAddr->CGCR1, SYS_CGCR1_PLL_PWRDN, CSL_FEXT(pconfigInfo->PLLCNTL1, SYS_CGCR1_PLL_PWRDN));
//CSL_FINST(hPll->sysAddr->CGCR1, SYS_CGCR1_PLL_PWRDN, POWERED);
/* Set RSVD = 1 in CGCR1 */
CSL_FINST(hPll->sysAddr->CGCR1, SYS_CGCR1_RSVD, SET);

/*Wait 4ms for the PLL to complete its phase-locking sequence*/
while (!PLL_getTestLockMonStatus(hPll) && timeout--) ;
/* Select pll */
CSL_FINST(hPll->sysAddr->CCR2, SYS_CCR2_SYSCLKSEL, LOCK);

return (status);
}

0 Junji Takahata over 13 years ago in reply to Juliana Mansell

Prodigy 40 points

Dear Mansell

Thank you for reply.

Build result output some error messages as below

identifier "CSL_SYS_CGCR1_RSVD_MASK" is undefined
identifier "CSL_SYS_CGCR1_RSVD_CLEAR" is undefined
identifier "CSL_SYS_CGCR1_RSVD_SHIFT" is undefined
identifier "CSL_SYS_CGCR1_M_MASK" is undefined
identifier "CSL_SYS_CGCR1_M_SHIFT" is undefined
identifier "CSL_SYS_CGCR1_RSVD_SET" is undefined

I found the macro of equation in "cslr.h".

But where can I get definitions itself ?

And also these errors below occur.

hPll->sysAddr->CGCR4 = pconfigInfo->PLLOUTCNTL;

--> struct "<unnamed>" has no field "CGCR4"

hPll->sysAddr->CGCR3 = pconfigInfo->PLLCNTL2;

--> Error: struct "<unnamed>" has no field "CGCR3"

Thanks.

0 Juliana Mansell over 13 years ago in reply to Junji Takahata

TI__Intellectual 1755 points

These are some changes in the cslr_sysctrl.h file. There will be a new release of the CSL in the next week. I will let you know once it is released for the latest download.

0 Junji Takahata over 13 years ago in reply to Juliana Mansell

Prodigy 40 points

Thank you for release information.

I tried to build with some modifications like ...

CGCR2 --> CGICR
CGCR3 --> CGCR2
CGCR4 --> CGOCR

and add definitions.

But it didn't work.

If software is fine, then

Is there any possibility of relation with hardware or emulator usage ?

Thanks.

0 Juliana Mansell over 13 years ago in reply to Junji Takahata

TI__Intellectual 1755 points

There are more changes involved than just the register names, which will be provided with the new release.

Processors

Processors forum

PLL Clock trouble