Hi All,
C_WEN Write enable signal used to store valid frame data in SDRAM.
External WEN MODESET.SWEN CCDCFG.WENLOG
External WEN Selection When set to 1 and when ENABLE is set to 1, the external WEN signal is
used as the external memory write enable (to SDRAM/DDRAM). The data is stored to memory only
when the external sync (HD and VD) signals are active. This bit should not be set if the
C_WE_Field bit is set.
WENLOG
Specifies CCD valid area
0 Internal valid and WEN signals are ANDed logically
1 Internal valid and WEN signals are ORed logically
my question:
Does many discrete WEN signals allowed In one line(valid HS)?
PCLK: ___----____----___----___----___
HS: ----________________________----
WEN: ___ _________
Thanks.