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About gpio_get_value In DM6467T

I took some test on DM6467T about DM6467T recently

I want to know my Read/Write operation for GPIO if correct, I make some contracts on my device with my hardware-engneer: GPIO0 is output, GPIO1,GPIO2,GPIO3,GPIO37 are input. If we set a value to GPIO0, this value will output to GPIO1,GPIO2,GPIO3,GPIO37.

my initiated code in kernel as following:

gpio_request(0, NULL) ;

gpio_request(1, NULL) ;

gpio_request(2, NULL) ;

gpio_request(3, NULL) ;

gpio_request(37, NULL) ;

.........

.........

gpio_direction_output(0, 0)  ;

gpio_direction_input(1)  ;

gpio_direction_input(2)  ;

gpio_direction_input(3)  ;

gpio_direction_input(37)  ;

Write operation as following:

gpio_set_value(0, 1) ;

Read operation as following:

unsigned int uValue1 = 0 ;

unsigned int uValue2 = 0 ;

unsigned int uValue3 = 0 ;

unsigned int uValue37 = 0 ;

uValue1= gpio_get_value(1) ;

uValue1 = (uValue1 >> 1) & 0x00000001 ;

uValue2 = gpio_get_value(2) ;

uValue2= (uValue2>> 2) & 0x00000001 ;

uValue3 = gpio_get_value(3) ;

uValue3= (uValue2>>3) & 0x00000001 ;

uValue37 = gpio_get_value(37) ;

uValue37= (uValue2>>5) & 0x00000001 ;

Result as following:

uValue1、uValue2、uValue3 are all 1,but uValue37 is always 0

I don't know why was that, GPIO37 need some special setting ? or say GPIOn(n >= 32) need some special setting?

Is there anyone give me some promption?

  • I don't have this processor. The datasheet would suggest that GP[37] is muxed to the UART0. Assuming default values in PINMUX0 and PINMUX1 then:

    Pin GP[0] -> always GP[0]
    Pin GP[1] -> always GP[1]
    Pin GP[2]/AUDIO_CLK1 -> default GP[2]
    Pin GP[3]/AUDIO_CLK0 -> default GP[3]
    Pin nUDSR0/TS0_PSTO/GP[37] -> default nUDSR0

    This processor has one of the more complicated mux schemes that I've seen. The Linux code poorly handles this complexity. Might be difficult to change without other pins being changed. Maybe try one of the other dedicated GPIO pins.