Trouble running EDAM3 transfer with McBSP Digital Loop Back on TMDXEVM6657L

Hi Steven,

For now, we will just use Length = 64.  Thank you.

I like to set up this EDMA3 interrupt through configurator?  What Event Id and Interrupt number should I use?

Thank you.

Regards,

Steve

Steve,

Sorry that the McBSP test setup was not available for past several days. I did not have chance to look into the EDMA length issue. I may take a look at it later.

For EDMA3 interrupt setup, are you planning to generate EDMA3 completion interrupt to CorePac please?

If so, and if you are using global region for EDMA3 setup, you can use system event 33 (EDMA3_CC_GINT) for CIC0 (table 7-34 in 6657 data manual) and it could be mapped to any CIC0 output (host event) which has the connection to CorePac (Table 7-33 in 6657 data manual).

If you are using shadow region for EDMA3, then you can use system events 24-31 which are for shadow region 0-7.

For the CPU INTC vectID, you can choose from 4 to 15. 

Section 2.9 in EDMA user guide and chapter 9 in C66x user guide should have more details regarding to this.

Hi Steven,

Yes, we need to generate EDMA3 completion interrupt to CorePac.  I used Event Id = 33 and my edma_rcv1 ISR did not get called.  I looked at Table 7-33.  33 is QM_INT_LOW_1, that is not EDMA3_CC_GINT.    Table 7-34 has EDMA3_CC_GINT = 22.   Could you tell me what are the settings for the configurator page?  I am quite confused by the documentation about this simple page, see below.

Thank you.

Regards,

Steve

Steve,

Sorry for that I looked at the wrong data manual. You are right that  it should be event 22 for EDMA3_CC_GINT in 6657. But the event number is the system event input number for CIC0. You need to map the system event to CIC0 host output, which is the input to CorePac INTC. So it is two-step procedure.

I think the BIOS page you are showing is for CorePac INTC (HWI) only. The interrupt number could be 4-15 (5 in your example). But the event ID is the input to CorePac INTC (event number in Table 7-33), not the system event number in table 7-34. For example, if you choose to map system event 22 (EDMA3_CC_GINT) to CIC0 host output 40, then you can use event ID 56 in this page, since CIC0_OUT40 is event 56 for CorePac (table 7-34).

You may need to setup both of the CIC and CorePac INTC your case.

There is one wiki page talks about the interrupt setup in C66x devices.

http://processors.wiki.ti.com/index.php/Configuring_Interrupts_on_Keystone_Devices#CpIntc

But it is mainly for the C code part in BIOS.

I am not familiar with BIOS CFG setup. If you would like to use the CFG page instead of C code, you may get quicker response when posting the question on BIOS E2E forum. Hope it helps.

Hello Steven,

Thanks for the support that I got the interrupt to work with EDMA3 and McBSP.   Now I have an anomally, every time, I need to do a complete system reset before running the code.  If I don't do a complete system reset (Ctrl Shift S),  interrupt doesn't happen.   How do I reset the interrupt in the code? 

Thank you.

Steve

Steve,

In your ISR, you need to clear the CIC system interrupt flag, the source event interrupt flag (EDMA) and the CorePac interrupt flag. Then the same event could be triggered again after you exit from ISR.

The CIC user guide has some example in section 2.3 Interrupt Servicing. 

If using CSL, the steps in ISR could be generally as follows. Please refer to the CSL document for the details of the usage.

/* Disable the CIC0 host interrupt output */
CSL_CPINTC_disableHostInterrupt(cphnd, host_event);

/* Clear the CIC0 system interrupt */
CSL_CPINTC_clearSysInterrupt(cphnd, sys_event);

/* Service the interrupt at source */

(clear and read back the source interrupt flag is typically the first step in the service)

CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR, &regionIntr)

......

/* Clear the CorePac interrupt */

CSL_intcHwControl(hIntcEvent[Event IDX],CSL_INTC_CMD_EVTCLEAR,NULL);

/* Enable the CIC0 host interrupt output */
CSL_CPINTC_enableHostInterrupt(cphnd, host_event);

Hi Steven,

Thanks for the quick reply.  I don't have problem with ISR.  My problem is when I RESTART my program without a complete reset(control-shift-S),  interrupt does not happen.

Thanks.

Steve

Steve,

The system reset will put the device back into default reset mode. Your program may try to re-initialize or re-configure the McBSP/EDMA/CIC modules when you restart. But without the system reset, those modules will hold the existing registers setup from your last run and the re-initialization may cause some conflict.

So it could be better to close or reset those modules at the end or the beginning of your application. For example, section 2.11 in McBSP user's guide talks about how to reset McBSP module. 

You may need to take step by step to debug why the interrupt has not been triggered. You can start with McBSP to see if it could generate event to EDMA, and then if EDMA could trigger CPU event and so on.

Hi Steven,

I am implementing EDMA3 with UART receive.   I just need EDMA3 to move UART received data to a circular buffer.  Software will take data out.  No interrupts.

After I setting up the EDMA3 with the UART Rx, I typed a few characters on the Hyper Terminal.  The EDMA3 does not move data at all. 

I used the platform_test's uart code to initialize UART peripherial.

What might be my problem?

Thank you.

Regards,

Steve

Steve,

I replied to your email on the same topic in another thread:

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/225788/891692.aspx#891692

If you would like, we can continue the discussion there. Thanks.