Trouble running EDAM3 transfer with McBSP Digital Loop Back on TMDXEVM6657L

/*****************************************************************************\
*           TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
*
*  Property of Texas Instruments
*  For  Unrestricted  Internal  Use  Only
*  Unauthorized reproduction and/or distribution is strictly prohibited.
*  This product is protected under copyright law and trade secret law
*  as an unpublished work.
*  Created 2011, (C) Copyright 2008 Texas Instruments.  All rights reserved.
*------------------------------------------------------------------------------
*  Filename       : tput_search_128ch_32bit.c
*  Date Created   : July 21, 2011
*  Last Modified  :
*  Description    : Checks the throughput of McBSP by running the testcase at 
*                      different clock frequencies and records first frequency
*                      the test case fails. McBSP transfer requests are routed
*                      through Config bus.
*  History        : Ported from CURIE
*  Project        : Gauss
*  Author         : Kanchana
\*****************************************************************************/
/* ** \Register Configurations:
 **   -# No Of Phase - 1,
 **   -# Word Length - 32,
 **   -# Frame Length  - 128,
 **   -# Data Delay  - 0,
 **   -# Interrupt on Mcbsp Transmitter and Receiver SYNC Error conditions. 
            EDMA Interrupts for Event Completion.
 **   -# XCLK --> RCLK, Internal XFS --> RFS
 **   -# Loop Back Mode  - DLB ON,
 **   -# Internal Frame Sync Generation from Sample Rate Generator
 **   -# Frame Sync Pulse Width  - 1,
 **   -# Frame Sync Period - 0xFFF for 128 Channels,
 **   -# Clock Divide Value - Variable,
 **   -# Enhanced Multi channel selection Enable (128 Channels)
 **   -#First run with FIFO disabled(CFG path), then with FIFO enabled(EDMA path)
  *************************************************************************/

/* CSL specific include files */
#include <csl.h>
#include <csl_edma3.h>
#include <csl_intc.h>
#include <csl_edma3Aux.h>
#include <cslr_device.h>
#include <cslr_mcbsp.h>
#include <csl_mcbsp.h>

#include <val_util.h>          /* Common utility specific */

/** Header files corresponding to MCBSP module*/
#include <mcbsp_common.h>      /* McBSP common functions */
#include <edma_mcbsp_common.h> /* EDMA common functions */
//#include <mcbsp_intr.h>        /* McBSP and EDMA Interrupt Setup and ISRs*/
#include <test_init.h>         /* Testcase specific */
#include <csl_mcbspAux.h>
#include <fifo.h>
#include <event_defines.h>
#include <stdio.h>

#include <ti/csl/csl_cache.h>
#include <ti/csl/csl_cacheAux.h>

#define CLKGDV_START_VALUE 0

#pragma DATA_SECTION(xmtBuff0, ".Xmt_data")  /* xmtBuff can be in L2, DDR or MSMC.Here it is in L2 */
Uint32 xmtBuff0[NUM_XMT_ELEMENTS];

#pragma DATA_SECTION(xmtBuff1,".Xmt_data")
Uint32 xmtBuff1[NUM_XMT_ELEMENTS];


#pragma DATA_SECTION(rcvBuff0, ".Rcv_data")  /* rcvBuff can be in L2, DDR or MSMC.Here it is in L2 */
Uint32 rcvBuff0[NUM_RCV_ELEMENTS];

#pragma DATA_SECTION(rcvBuff1, ".Rcv_data")
Uint32 rcvBuff1[NUM_RCV_ELEMENTS];

#pragma DATA_SECTION(profile_results, ".msmcData")
Uint32 profile_results[500];

Uint32 MCBSP0_BASE_ADDRESS;
//Uint32 profile_results[];
Uint32 *profileresultsPtr;

CSL_Status status;						/* CSL status variable */

CSL_McbspIntMode mytxInt,myrxInt;       /* interrupt scratchpad variables */

CSL_BitMask32 secEventLo = -1;
CSL_BitMask32 secEventHi = -1;
CSL_BitMask32 missedLo = -1;
CSL_BitMask32 missedHi = -1;
CSL_BitMask32 missedQdma = -1;

extern fifo_info myfifo;


Uint32 main(void)
{
	Uint32 failFlag = 0;
	    Uint32 mcbspError = 0;
	    Uint32 intrEn[2] = {0,0};
	    Uint32 i = 0, j, k;
	    Uint32 mcbsp1_spcr = 0, mcbsp0_spcr = 0;
	    Uint32 edma_done = 0, sync_error = 0;
	    Uint32 result;
	    Uint32 err_val = 0;
	    Uint32 no_of_elements;
	    //Uint32 no_of_receive_elements;
	    Uint32 MCBSP0_BASE_ADDRESS, MCBSP1_BASE_ADDRESS;
	    volatile Uint32 * writeAddress0;
	    volatile Uint32 * writeAddress1;
	    volatile Uint32 * readAddress0;
	    volatile Uint32 * readAddress1;
	    Uint32 * xmtBuff0_global;
	    Uint32 * rcvBuff0_global;
	    Uint32 * xmtBuff1_global;
	    Uint32 * rcvBuff1_global;

	    Uint32 temp_TCC_Tx[2];
	    Uint32 temp_TCC_Rx[2];
	    CSL_Edma3CmdIntr  ipr;
	    Uint32 Mcbsp0_Tx_Edma_Done = 0;
	    Uint32 Mcbsp0_Rcv_Edma_Done = 0;
	    Uint32 Mcbsp1_Tx_Edma_Done = 0;
	    Uint32 Mcbsp1_Rcv_Edma_Done = 0;
	    Uint32 Xfr_Complete_Code_Mcbsp_Tx[2] = {CSL_EDMACC_2_CHA_XEVT0,CSL_EDMACC_2_CHA_XEVT1};
	    Uint32 Xfr_Complete_Code_Mcbsp_Rx[2] = {CSL_EDMACC_2_CHA_REVT0,CSL_EDMACC_2_CHA_REVT1};
	    Uint32 acnt, bcnt,srcBIDX,dstBIDX;


	//Since internal clock coming to Mcbsp is CPU/6=166.67MHz,max freq upto which we can check is 83.34MHz
	    Uint32 Mcbsp_Div[MAX_ITERATIONS]={0x3,0x2,0x1,0x0};

	    //disable L1D/L2 cache
		CACHE_setL1DSize(CACHE_L1_0KCACHE);
		CACHE_setL2Size(CACHE_0KCACHE);

	    VAL_TRACE(0xAAAA0000);

	   profileresultsPtr = (Uint32 *)profile_results;  /* Assign Results array to the pointer */

	   /* for loop for the various iterations...In 1st iteration FIFO is disabled..In 2nd iteration
	    FIFO is enabled but with WNUM_EVT/RNUM_EVT =1 word..i.e there is no effect of FIFO usage..
	    In the following iterations WNUM_EVT/RNUM_EVT value is gradually increased in multiples of 8
	    i.e.  8,16, 24..upto 64 words which is the max*/
	   EDMA3_ModuleInitOpen();     			 /* Initialize the EDMA Module and open a handle */

	      CSL_mcbspInit(0);						 /* Initialize the MCBSP CSL */

	 for(j=0;j<NUM_OF_ITERATIONS;j++)
	  {
		 failFlag = 0;


	     VAL_TRACE(0xAAAA0002);

	   /*Initialise all the Mcbsp and EDMA handles to NULL */
	    hMcbsp0ChTx = NULL; hMcbsp0ChRx = NULL; hParamMcbsp0Tx = NULL; hParamMcbsp0Rx = NULL;
	    hMcbsp1ChTx = NULL; hMcbsp1ChRx = NULL; hParamMcbsp1Tx = NULL; hParamMcbsp1Rx = NULL;

	    /*Open, Reset and Configure the McBSP Handle  */
	   hMcbsp[0] = CSL_mcbspOpen(&myMcbspObj[0],
	                                  CSL_MCBSP_PERI[0],
	                                  NULL,
	                                  &status);

	   hMcbsp[1] = CSL_mcbspOpen(&myMcbspObj[1],
	                                  CSL_MCBSP_PERI[1],
	                                  NULL,
	                                  &status);

	    /*Open the EMDA Handles for McBSP0 and McBSP1 Channels*/
	    EDMA_Mcbsp_ChannelOpen(CSL_MCBSP_A, EDMA_MCBSP_CHA_TX_DIR, &hMcbsp0ChTx);

	    EDMA_Mcbsp_ChannelOpen(CSL_MCBSP_A, EDMA_MCBSP_CHA_RX_DIR, &hMcbsp0ChRx);

	    EDMA_Mcbsp_ChannelOpen(CSL_MCBSP_B, EDMA_MCBSP_CHA_TX_DIR, &hMcbsp1ChTx);
	    EDMA_Mcbsp_ChannelOpen(CSL_MCBSP_B, EDMA_MCBSP_CHA_RX_DIR, &hMcbsp1ChRx);

	    /* Initialize Data for TX and corrupt RX buffer       */
	    Fill_McBSP_DataBuffer_Multichannel((Uint8 *)xmtBuff0,(Uint8 *) rcvBuff0, NUM_XMT_ELEMENTS);
	    Fill_McBSP_DataBuffer_Multichannel((Uint8 *)xmtBuff1, (Uint8 *)rcvBuff1, NUM_XMT_ELEMENTS);

	    /*Since there is only DXR or DRR register to write/read WNUMDMA/RNUMDMA =1 */

	  //  no_of_xmt_elements      = 128;
	//    no_of_receive_elements  = 128;

	    switch(j)
	    {
	    case(0):
	    	{
	    	myfifo.WriteFifoEnable	= 0;
	        myfifo.ReadFifoEnable	= 0;
	        no_of_elements = 512; //total no. of bytes of transfer
	        acnt = 4;
	        bcnt = (no_of_elements/acnt);
	        srcBIDX = acnt;
	        dstBIDX = 0;

	        break;
	        }
	    case(1):
	    	{
	    	myfifo.WriteFifoEnable	= 1;
	    	myfifo.ReadFifoEnable	= 1;
	    	myfifo.TEST_WNUMEVT     = 32;
	    	myfifo.TEST_RNUMEVT	    = 32;
	    	myfifo.TEST_WNUMDMA	    = 1;
	    	myfifo.TEST_RNUMDMA	    = 1;

	    	no_of_elements = 512; //total no. of bytes of transfer
	    	acnt = (myfifo.TEST_WNUMEVT *4);
	    	bcnt = no_of_elements/acnt;
	    	srcBIDX = acnt;
	    	dstBIDX = acnt;

	        break;
	    	}
	    default:
	        	break;
	        }


	    if(myfifo.WriteFifoEnable ==1 || myfifo.ReadFifoEnable ==1)
	        {
	        	 MCBSP0_BASE_ADDRESS= 0x22000000;
	        	 MCBSP1_BASE_ADDRESS= 0x22400000;

	        	 writeAddress0 = (Uint32 *)(MCBSP0_BASE_ADDRESS + 0x00000004); //DXR offset for the DMA path is 0x04
	        	 readAddress0  = (Uint32 *)(MCBSP0_BASE_ADDRESS + 0x00000000); //DRR offset for the DMA path is 0x00
	        	 writeAddress1 = (Uint32 *)(MCBSP1_BASE_ADDRESS + 0x00000004);
	        	 readAddress1  = (Uint32 *)(MCBSP1_BASE_ADDRESS + 0x00000000);
	        }
	    else
	        {
	        	 MCBSP0_BASE_ADDRESS= 0x021B4000;
	        	 MCBSP1_BASE_ADDRESS= 0x021B8000;

	        	 writeAddress0 = (Uint32 *)(MCBSP0_BASE_ADDRESS + 0x00000004); //DXR offset for the CPU path is 0x04
	        	 readAddress0  = (Uint32 *)(MCBSP0_BASE_ADDRESS + 0x00000000); //DRR offset for the CPU path is 0x00
	        	 writeAddress1 = (Uint32 *)(MCBSP1_BASE_ADDRESS + 0x00000004);
	             readAddress1  = (Uint32 *)(MCBSP1_BASE_ADDRESS + 0x00000000);
	        }


	     /* Enable the events on the EDMA*/


	    intrEn[0] = (1 << (Xfr_Complete_Code_Mcbsp_Tx[0]));
	    CSL_edma3HwChannelControl(hMcbsp0ChTx, CSL_EDMA3_CMD_CHANNEL_ENABLE, intrEn);
	    intrEn[0] = (1 << (Xfr_Complete_Code_Mcbsp_Rx[0]));
	    CSL_edma3HwChannelControl(hMcbsp0ChRx, CSL_EDMA3_CMD_CHANNEL_ENABLE, intrEn);
	    intrEn[0] = (1 << (Xfr_Complete_Code_Mcbsp_Tx[1]));
	    CSL_edma3HwChannelControl(hMcbsp1ChTx, CSL_EDMA3_CMD_CHANNEL_ENABLE, intrEn);
	    intrEn[0] = (1 << (Xfr_Complete_Code_Mcbsp_Rx[1]));
	    CSL_edma3HwChannelControl(hMcbsp1ChRx, CSL_EDMA3_CMD_CHANNEL_ENABLE, intrEn);

	    temp_TCC_Tx[0] =  (Xfr_Complete_Code_Mcbsp_Tx[0]-32);
	    temp_TCC_Tx[1] =  (Xfr_Complete_Code_Mcbsp_Tx[1]-32);
	    temp_TCC_Rx[0] =  (Xfr_Complete_Code_Mcbsp_Rx[0]-32);
	    temp_TCC_Rx[1] =  (Xfr_Complete_Code_Mcbsp_Rx[1]-32);

	    ipr.region=CSL_EDMA3_REGION_GLOBAL;
	         	 	 ipr.intrh= (1 << temp_TCC_Tx[0])\
	                         |(1 << temp_TCC_Tx[1])\
	                         |(1 << temp_TCC_Rx[0])\
	                         |(1 << temp_TCC_Rx[1]);

	    CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,&ipr);

	   xmtBuff0_global = (Uint32 *) global_address((Uint32)xmtBuff0);
	   rcvBuff0_global = (Uint32 *) global_address((Uint32)rcvBuff0);
	   xmtBuff1_global = (Uint32 *) global_address((Uint32)xmtBuff1);
	   rcvBuff1_global = (Uint32 *) global_address((Uint32)rcvBuff1);

	   // Wait for interrupt
       ipr.region  = CSL_EDMA3_REGION_GLOBAL;
       ipr.intr    = 0;
       ipr.intrh   = 0;

	    /* Iteration number varies from 0 to CLKGDV_START_VALUE */
	    for(i = 0; i <MAX_ITERATIONS; i++)
	    {
	        VAL_TRACE(0xcace1100 + i);

	        /* Reset the MCBSP Channel  */
	        CSL_mcbspHwControl (hMcbsp[0], CSL_MCBSP_CMD_RESET, 0);
	        CSL_mcbspHwControl (hMcbsp[1], CSL_MCBSP_CMD_RESET, 0);

	        /* configure for 128 channel mode*/
	        Configure_MultiChannel(CSL_MCBSP_A, xmt_channels, rcv_channels);
	        Configure_MultiChannel(CSL_MCBSP_B, xmt_channels, rcv_channels);

	        MCBSP_HwSetupStructFill(Mcbsp_Div[i]); /* Populate the McBSP parameters into local structure */

	        /* Fill RX buffer for both the McBSP's with zeroes */
	        Corrupt_McBSP_DataBuffer(rcvBuff0, NUM_RCV_ELEMENTS);
	        Corrupt_McBSP_DataBuffer(rcvBuff1, NUM_RCV_ELEMENTS);

	        CSL_mcbspHwSetup(hMcbsp[0], &mySetup); /* Configure the Mcbsp registers */
	        CSL_mcbspHwSetup(hMcbsp[1], &mySetup);


	        Edma_Mcbsp_Setup (CSL_MCBSP_A,           /*      Setup the EMDA for McBSP0              */
	        		          readAddress0,
	        		          writeAddress0,
	                          &hMcbsp0ChTx,
	                          &hMcbsp0ChRx,
	                          &hParamMcbsp0Tx,
	                          &hParamMcbsp0Rx,
	                          xmtBuff0_global,
	                          rcvBuff0_global,
	                          Xfr_Complete_Code_Mcbsp_Tx[0],
	                          Xfr_Complete_Code_Mcbsp_Rx[0],
	                          acnt,
	                          bcnt,
	                          srcBIDX,
	                          dstBIDX);

	        Edma_Mcbsp_Setup (CSL_MCBSP_B,            /*      Setup the EMDA for McBSP1              */
	        				  readAddress1,
	        		          writeAddress1,
	                          &hMcbsp1ChTx,
	                          &hMcbsp1ChRx,
	                          &hParamMcbsp1Tx,
	                          &hParamMcbsp1Rx,
	                          xmtBuff1_global,
	                          rcvBuff1_global,
	                          Xfr_Complete_Code_Mcbsp_Tx[1],
	                          Xfr_Complete_Code_Mcbsp_Rx[1],
	                          acnt,
	                          bcnt,
	                          srcBIDX,
	                          dstBIDX);


	        /*Initialize the FIFO*/
	        InitBfifo_0(myfifo.TEST_WNUMDMA, myfifo.TEST_WNUMEVT, myfifo.TEST_RNUMDMA, myfifo.TEST_RNUMEVT);
	        InitBfifo_1(myfifo.TEST_WNUMDMA, myfifo.TEST_WNUMEVT, myfifo.TEST_RNUMDMA, myfifo.TEST_RNUMEVT);

	        VAL_TRACE(0x98989898);

	        for(k=0; k <= 50; k++); //adding delay

	        Tx_Rx_Clkgen_Frmgen(hMcbsp[0], MCBSP_ENABLE);   /*Enable TX, RX, SRGR clock and SRGR Frame generation */
	        Tx_Rx_Clkgen_Frmgen(hMcbsp[1], MCBSP_ENABLE);

	        VAL_TRACE(0x99990000);



	        do
	                  {
	                      CSL_edma3GetHwStatus(hModule,
	                  		        CSL_EDMA3_QUERY_INTRPEND,
	                  		        &ipr);
	                  }while(ipr.intrh!= 0x000000F0);

	                      if(ipr.intrh & (1 << temp_TCC_Tx[0]))
	                      {
	                          Mcbsp0_Tx_Edma_Done = 1;
	                          VAL_TRACE(0xedcb0000 + temp_TCC_Tx[0]);
	                      }
	                      if(ipr.intrh & (1 << temp_TCC_Tx[1]))
	                      {
	                          Mcbsp1_Tx_Edma_Done = 1;
	                          VAL_TRACE(0xedcb1000 + temp_TCC_Tx[1]);

	                      }
	                      if(ipr.intrh & (1 << temp_TCC_Rx[0]))
	                      {
	                          Mcbsp0_Rcv_Edma_Done = 1;
	                          VAL_TRACE(0xedcb0100 + temp_TCC_Rx[0]);
	                      }
	                      if(ipr.intrh & (1 << temp_TCC_Rx[1]))
	                      {
	                          Mcbsp1_Rcv_Edma_Done = 1;
	                          VAL_TRACE(0xedcb1100 + temp_TCC_Rx[1]);
	                      }

	                      CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR,&ipr);
	               //   }while(ipr.intrh!= 0);

	                  /* Set Interrupt EVAL */
	                  ipr.intr  = 0x00000000;
	                  ipr.intrh = 0x00000000;

	edma_done = Mcbsp0_Tx_Edma_Done + Mcbsp0_Rcv_Edma_Done + Mcbsp1_Tx_Edma_Done + Mcbsp1_Rcv_Edma_Done;


		/* Disable TX, RX, SRGR clock and SRGR Frame generation */
	        Tx_Rx_Clkgen_Frmgen(hMcbsp[0], MCBSP_DISABLE);
	        Tx_Rx_Clkgen_Frmgen(hMcbsp[1], MCBSP_DISABLE);

	        VAL_TRACE(0xeeee0000 + mcbspError);

	        failFlag =0;
	        /* Data comparison for McBSP0 and McBSP1 */
	     ////   if(mcbspError == 0)
	     //   {
	            failFlag = Compare_McBSP_DataBuffer_MultiChannel(xmtBuff0,
	                                                              rcvBuff0,
	                                                              NUM_XFR_ITERATIONS,
	                                                              FRAME_LENGTH1,
	                                                              xmt_channels,
	                                                              rcv_channels,
	                                                              mytxdata.wordLength1,
	                                                              mytxdata.rjust_dxenable);

	            failFlag = (failFlag & (Compare_McBSP_DataBuffer_MultiChannel(xmtBuff1,
	                                                              rcvBuff1,
	                                                              NUM_XFR_ITERATIONS,
	                                                              FRAME_LENGTH1,
	                                                              xmt_channels,
	                                                              rcv_channels,
	                                                              mytxdata.wordLength1,
	                                                              mytxdata.rjust_dxenable)));
	        VAL_TRACE(0xAAAAABCD);

	        if (failFlag != PASS)
	           {
	               VAL_TRACE(0xDEAD0000 + i);
	               VAL_TRACE(mcbsp0_spcr);
	               VAL_TRACE(mcbsp1_spcr);
	               *(profileresultsPtr++) = i;  //Store iteration number i
	               *(profileresultsPtr++) = j;
	               VAL_TRACE(myclkset.srgClkDivide);
	               *(profileresultsPtr++) = Mcbsp_Div[i]; //Store corresponding CLKGDV value
	               *(profileresultsPtr++) = 0xDEADDEAD;
	               result = FAIL;
	           }
	           else
	           {
	               VAL_TRACE(0xABCDABCD);
	               *(profileresultsPtr++) = i;  //Store iteration number i
	               *(profileresultsPtr++) = j;
	               VAL_TRACE(myclkset.srgClkDivide);
	               *(profileresultsPtr++) = Mcbsp_Div[i]; //Store corresponding CLKGDV value
	               *(profileresultsPtr++) = 0xABCDABCD;
	               result = PASS;
	           }
	        /* Clear SEC bits corresponding to EDMA Channel numbers used by writing into SECR register.
	         This is to be repeated for every iteration */

	        CSL_edma3ClearDMASecondaryEvents(hModule,secEventLo,secEventHi);
	        CSL_edma3EventsMissedClear(hModule,missedLo, missedHi, missedQdma);


		    Mcbsp0_Tx_Edma_Done = 0; Mcbsp0_Rcv_Edma_Done = 0;
	        Mcbsp1_Tx_Edma_Done = 0; Mcbsp1_Rcv_Edma_Done = 0;

	 //       rxd_cnt0 = 0; txd_cnt0 = 0; rxd_cnt1 = 0; txd_cnt1 = 0;
	        edma_done = 0; sync_error = 0;
	    } // end... for(i = 0; (i <= (CLKGDV_START_VALUE - 1)) && (mcbspError == 0); i++)

	  }

	    /* Close the EDMA channel opened for McBSP Transmit and Recieve */
	    EDMA_Mcbsp_ChannelClose(&hMcbsp0ChTx, &hMcbsp0ChRx);
	    EDMA_Mcbsp_ChannelClose(&hMcbsp1ChTx, &hMcbsp1ChRx);

	    status = CSL_mcbspClose(hMcbsp[0]);      /* Close the McBSP Handle*/
	    status = CSL_mcbspClose(hMcbsp[1]);

	    CSL_edma3Close(hModule);                    /* Close the EDMA Module*/



	    if (result == PASS)
	    	printf("Test passed\n");
	    else
	    	printf("Test failed\n");

	  return(result);
	}



	void MCBSP_HwSetupStructFill(Uint32 ClkDiv)
	{
	    /*************************************************************************/
	        /* \brief  Configure the MCBSP with following values.
		*************************************************************************
		** \note McBSP receiver, transmitter frame sync logic and sample rate
	 	** generator are not enabled in this function. This is done because
	 	** once these are enabled, McBSP will start its operation, which might
	 	** not be required till DMA and IRQ setups, if any are done.
	 	*************************************************************************/

	        myglobal.ioEnableMode                 =    CSL_MCBSP_IOMODE_TXDIS_RXDIS;

	#ifdef TB_LOOPBACK
	        myglobal.dlbMode                      =    CSL_MCBSP_DLBMODE_OFF;
	#else
		    myglobal.dlbMode                      =    CSL_MCBSP_DLBMODE_ON;    // DLB mode
	#endif

	        myglobal.clkStopMode                  =    CSL_MCBSP_CLKSTP_DISABLE;

	        myrxdata.wordReverse 	              =    CSL_MCBSP_32BIT_REVERS_DISABLE;
	        myrxdata.numPhases 	                  =    CSL_MCBSP_PHASE_SINGLE;
	        myrxdata.wordLength1 	              =    CSL_MCBSP_WORDLEN_32;
	        myrxdata.frmLength1        	          =	   FRAME_LENGTH1;
	        myrxdata.wordLength2	              =    CSL_MCBSP_WORDLEN_8;
	        myrxdata.frmLength2  	              =    FRAME_LENGTH2;
	        myrxdata.frmSyncIgn	 	              =    CSL_MCBSP_FRMSYNC_DETECT;
	        myrxdata.compand 		              =    CSL_MCBSP_COMPAND_OFF_MSB_FIRST;
	        myrxdata.dataDelay 	                  =    CSL_MCBSP_DATADELAY_0_BIT;
	        myrxdata.rjust_dxenable 	          =    CSL_MCBSP_RJUSTDXENA_RJUST_RZF;
	        myrxdata.intEvent 		              =    CSL_MCBSP_INTMODE_ON_SYNCERR; // RINTM of SPCR . Value is 2'b11

	        mytxdata.wordReverse 	              =    CSL_MCBSP_32BIT_REVERS_DISABLE;
	        mytxdata.numPhases 	                  =    CSL_MCBSP_PHASE_SINGLE;
	        mytxdata.wordLength1 	              =    CSL_MCBSP_WORDLEN_32;
	        mytxdata.frmLength1                   =    FRAME_LENGTH1;
	        mytxdata.wordLength2		          =    CSL_MCBSP_WORDLEN_8;
	        mytxdata.frmLength2  	              =    FRAME_LENGTH2;
	        mytxdata.frmSyncIgn	 	              =    CSL_MCBSP_FRMSYNC_DETECT;
	        mytxdata.compand 		              =    CSL_MCBSP_COMPAND_OFF_MSB_FIRST;
	        mytxdata.dataDelay 		              =    CSL_MCBSP_DATADELAY_0_BIT;
	        mytxdata.rjust_dxenable 	          =    CSL_MCBSP_RJUSTDXENA_RJUST_RZF;
	        mytxdata.intEvent 		              =    CSL_MCBSP_INTMODE_ON_FSYNC;    //XINTM OF SPCR.Value is 2'b10


	        myclkset.frmSyncTxMode 		          =    CSL_MCBSP_FSCLKMODE_INTERNAL; // Refers to FSXM field of PCR register
	        myclkset.frmSyncRxMode	          =    CSL_MCBSP_FSCLKMODE_EXTERNAL;  // Refers to FSRM field of PCR register
	       // myclkset.frmSyncRxMode	              =	   CSL_MCBSP_FSCLKMODE_INTERNAL;
	        myclkset.clkRxMode		              =    CSL_MCBSP_TXRXCLKMODE_EXTERNAL;	  // Refers to CLKRM field of PCR register
	        myclkset.clkTxMode		              =    CSL_MCBSP_TXRXCLKMODE_INTERNAL;    // Refers to CLKXM field of PCR register
	        myclkset.frmSyncTxPolarity	          =    CSL_MCBSP_FSPOL_ACTIVE_LOW;   	  //Refers to FSXP field of PCR register
	        myclkset.frmSyncRxPolarity	          =    CSL_MCBSP_FSPOL_ACTIVE_LOW;  	   //Refers to FSRP field of PCR register
	        myclkset.clkTxPolarity		          =    CSL_MCBSP_CLKPOL_TX_FALLING_EDGE; //Refers to CLKXP field of PCR register
	        myclkset.clkRxPolarity		          =    CSL_MCBSP_CLKPOL_RX_RISING_EDGE;  //Refers to CLKRP field of PCR register
			myclkset.srgClkDivide                 =    ClkDiv ;     					//CLKGDIV OF  SRGR

	        myclkset.srgFrmPulseWidth	          =    FRAME_PULSE_WIDTH;      //FWID OF SRGR
	        myclkset.srgFrmPeriod		          =    FRAME_PERIOD;           //FPER OF SRGR

	        //myclkset.srgInputClkMode	          =    CSL_MCBSP_SRGCLK_CLKS;  		//CLKSM OF SGRGR i.e External clock source.
	        myclkset.srgInputClkMode	          =    CSL_MCBSP_SRGCLK_CLKCPU;     //Change from external clk to CPU clock
	        myclkset.srgClkPolarity		          =    CSL_MCBSP_CLKPOL_SRG_RISING_EDGE;  //CLKSP OF SRGR


	        myclkset.srgTxFrmSyncMode	          =    CSL_MCBSP_TXFSMODE_SRG;   // FSGM OF SRGR


	        myclkset.srgClkSync		              =    CSL_MCBSP_CLKGSYNCMODE_OFF;  //GSYNC OF SRGR

	        mymulCh.rxPartition		              =    CSL_MCBSP_PARTMODE_8PARTITION;  //All 128 Channels are enabled
	        mymulCh.txPartition		              =    CSL_MCBSP_PARTMODE_8PARTITION;
	        mymulCh.rxMulChSel		              =    CSL_MCBSP_MULTI_CHANNEL_RX_EN_ALL; // RMCM =0 in MCR register
	        mymulCh.txMulChSel		              =    CSL_MCBSP_MULTI_CHANNEL_TX_EN_NO_MASK;  //XMCM =2'b01 in MCR reg
	        mymulCh.rxPartABlk		              =    CSL_MCBSP_PABLK_0;
	        mymulCh.rxPartBBlk		              =    CSL_MCBSP_PBBLK_1;
	        mymulCh.txPartABlk		              =    CSL_MCBSP_PABLK_0;
	        mymulCh.txPartBBlk		              =    CSL_MCBSP_PBBLK_1;
	        //mySetup.emumode			              =    CSL_MCBSP_EMU_STOP;
	        mySetup.emumode			              =    CSL_MCBSP_EMU_FREERUN;
	        mySetup.global                        =    &myglobal;
	        mySetup.rxdataset                     =    &myrxdata;
	        mySetup.txdataset                     =    &mytxdata;
	        mySetup.clkset                        =    &myclkset;
	        mySetup.mulCh                         =    &mymulCh;

	}

/*****************************************************************************\
*           TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
*
*  Property of Texas Instruments
*  For  Unrestricted  Internal  Use  Only
*  Unauthorized reproduction and/or distribution is strictly prohibited.
*  This product is protected under copyright law and trade secret law
*  as an unpublished work.
*  Created 2011, (C) Copyright 2008 Texas Instruments.  All rights reserved.
*------------------------------------------------------------------------------
*  Filename       : tput_search_128ch_32bit.c
*  Date Created   : July 21, 2011
*  Last Modified  :
*  Description    : Checks the throughput of McBSP by running the testcase at
*                      different clock frequencies and records first frequency
*                      the test case fails. McBSP transfer requests are routed
*                      through Config bus.
*  History        : Ported from CURIE
*  Project        : Gauss
*  Author         : Kanchana
\*****************************************************************************/
/* ** \Register Configurations:
 **   -# No Of Phase - 1,
 **   -# Word Length - 32,
 **   -# Frame Length  - 128,
 **   -# Data Delay  - 0,
 **   -# Interrupt on Mcbsp Transmitter and Receiver SYNC Error conditions.
            EDMA Interrupts for Event Completion.
 **   -# XCLK --> RCLK, Internal XFS --> RFS
 **   -# Loop Back Mode  - DLB ON,
 **   -# Internal Frame Sync Generation from Sample Rate Generator
 **   -# Frame Sync Pulse Width  - 1,
 **   -# Frame Sync Period - 0xFFF for 128 Channels,
 **   -# Clock Divide Value - Variable,
 **   -# Enhanced Multi channel selection Enable (128 Channels)
 **   -#First run with FIFO disabled(CFG path), then with FIFO enabled(EDMA path)
  *************************************************************************/

/* CSL specific include files */
#include <csl.h>
#include <csl_edma3.h>
#include <csl_intc.h>
#include <csl_edma3Aux.h>
#include <cslr_device.h>
#include <cslr_mcbsp.h>
#include <csl_mcbsp.h>

#include <val_util.h>          /* Common utility specific */

/** Header files corresponding to MCBSP module*/
#include <mcbsp_common.h>      /* McBSP common functions */
#include <edma_mcbsp_common.h> /* EDMA common functions */
//#include <mcbsp_intr.h>        /* McBSP and EDMA Interrupt Setup and ISRs*/
#include <test_init.h>         /* Testcase specific */
#include <csl_mcbspAux.h>
#include <fifo.h>
#include <event_defines.h>
#include <stdio.h>

#include <ti/csl/csl_cache.h>
#include <ti/csl/csl_cacheAux.h>

// SQ #define CLKGDV_START_VALUE 0
//Uint16 xmt_channels[] = {0xFFFF,0xFFFF,0xFFFF,0xFFFF,0xFFFF,0xFFFF,0xFFFF,0xFFFF};
//Uint16 rcv_channels[] = {0xFFFF,0xFFFF,0xFFFF,0xFFFF,0xFFFF,0xFFFF,0xFFFF,0xFFFF};
Uint16 xmt_channels[] = {0xFFFF,0xFFFF,0,0,0,0,0,0};
Uint16 rcv_channels[] = {0xFFFF,0xFFFF,0,0,0,0,0,0};

#pragma DATA_SECTION(xmtBuff0, ".Xmt_data")  /* xmtBuff can be in L2, DDR or MSMC.Here it is in L2 */
Uint32 xmtBuff0[NUM_XMT_ELEMENTS];

#pragma DATA_SECTION(xmtBuff1,".Xmt_data")
Uint32 xmtBuff1[NUM_XMT_ELEMENTS];


#pragma DATA_SECTION(rcvBuff0, ".Rcv_data")  /* rcvBuff can be in L2, DDR or MSMC.Here it is in L2 */
Uint32 rcvBuff0[NUM_RCV_ELEMENTS];

#pragma DATA_SECTION(rcvBuff1, ".Rcv_data")
Uint32 rcvBuff1[NUM_RCV_ELEMENTS];

#pragma DATA_SECTION(profile_results, ".msmcData")
Uint32 profile_results[500];

Uint32 MCBSP0_BASE_ADDRESS;
//Uint32 profile_results[];
Uint32 *profileresultsPtr;

CSL_Status status;						/* CSL status variable */

CSL_McbspIntMode mytxInt,myrxInt;       /* interrupt scratchpad variables */

CSL_BitMask32 secEventLo = 0xFFFFFFFF;
CSL_BitMask32 secEventHi = 0xFFFFFFFF;
CSL_BitMask32 missedLo   = 0xFFFFFFFF;
CSL_BitMask32 missedHi   = 0xFFFFFFFF;
CSL_BitMask32 missedQdma = 0xFFFFFFFF;

extern fifo_info myfifo;

void FPGA_main(void);

/******************************************************************************/
Uint32 old_main(void);
Uint32 main(void)
{
    FPGA_main();
    while (1)
        old_main();
}
/******************************************************************************/
Uint32 old_main(void)
{
	Uint32 failFlag = 0;
	    Uint32 mcbspError = 0;
	    Uint32 intrEn[2] = {0,0};
        Uint32 i = 0, j, k;
	    Uint32 mcbsp1_spcr = 0, mcbsp0_spcr = 0;
	    Uint32 edma_done = 0, sync_error = 0;
	    Uint32 result;
	    Uint32 err_val = 0;
	    Uint32 no_of_elements;
	    //Uint32 no_of_receive_elements;
	    Uint32 MCBSP0_BASE_ADDRESS, MCBSP1_BASE_ADDRESS;
	    volatile Uint32 * writeAddress0;
	    volatile Uint32 * writeAddress1;
	    volatile Uint32 * readAddress0;
	    volatile Uint32 * readAddress1;
	    Uint32 * xmtBuff0_global;
	    Uint32 * rcvBuff0_global;
	    Uint32 * xmtBuff1_global;
	    Uint32 * rcvBuff1_global;

	    Uint32 temp_TCC_Tx[2];
	    Uint32 temp_TCC_Rx[2];
	    CSL_Edma3CmdIntr  ipr;
	    Uint32 Mcbsp0_Tx_Edma_Done = 0;
	    Uint32 Mcbsp0_Rcv_Edma_Done = 0;
	    Uint32 Mcbsp1_Tx_Edma_Done = 0;
	    Uint32 Mcbsp1_Rcv_Edma_Done = 0;
	    Uint32 Xfr_Complete_Code_Mcbsp_Tx[2] = {CSL_EDMACC_2_CHA_XEVT0,CSL_EDMACC_2_CHA_XEVT1};
	    Uint32 Xfr_Complete_Code_Mcbsp_Rx[2] = {CSL_EDMACC_2_CHA_REVT0,CSL_EDMACC_2_CHA_REVT1};
	    Uint32 acnt, bcnt,srcBIDX,dstBIDX;

	//Since internal clock coming to Mcbsp is CPU/6=166.67MHz,max freq upto which we can check is 83.34MHz
       Uint32 Mcbsp_Div[MAX_ITERATIONS]={0x3,0x2,0x1,0x1};
//        Uint32 Mcbsp_Div[MAX_ITERATIONS]={0x1,0x1,0x1,0x1};

	    //disable L1D/L2 cache
		CACHE_setL1DSize(CACHE_L1_0KCACHE);
		CACHE_setL2Size(CACHE_0KCACHE);

	    VAL_TRACE(0xAAAA0000);

	   profileresultsPtr = (Uint32 *)profile_results;  /* Assign Results array to the pointer */

	   /* for loop for the various iterations...In 1st iteration FIFO is disabled..In 2nd iteration
	    FIFO is enabled but with WNUM_EVT/RNUM_EVT =1 word..i.e there is no effect of FIFO usage..
	    In the following iterations WNUM_EVT/RNUM_EVT value is gradually increased in multiples of 8
	    i.e.  8,16, 24..upto 64 words which is the max*/
	   EDMA3_ModuleInitOpen();     			 /* Initialize the EDMA Module and open a handle */

	      CSL_mcbspInit(0);						 /* Initialize the MCBSP CSL */

//    for(j=0;j<NUM_OF_ITERATIONS;j++)
     for(j = 1; j < NUM_OF_ITERATIONS; j++)
	  {
		 failFlag = 0;


	     VAL_TRACE(0xAAAA0002);

	   /*Initialise all the Mcbsp and EDMA handles to NULL */
	    hMcbsp0ChTx = NULL; hMcbsp0ChRx = NULL; hParamMcbsp0Tx = NULL; hParamMcbsp0Rx = NULL;
	    hMcbsp1ChTx = NULL; hMcbsp1ChRx = NULL; hParamMcbsp1Tx = NULL; hParamMcbsp1Rx = NULL;

	    /*Open, Reset and Configure the McBSP Handle  */
	   hMcbsp[0] = CSL_mcbspOpen(&myMcbspObj[0],
	                                  CSL_MCBSP_PERI[0],
	                                  NULL,
	                                  &status);

	   hMcbsp[1] = CSL_mcbspOpen(&myMcbspObj[1],
	                                  CSL_MCBSP_PERI[1],
	                                  NULL,
	                                  &status);

	    /*Open the EMDA Handles for McBSP0 and McBSP1 Channels*/
	    EDMA_Mcbsp_ChannelOpen(CSL_MCBSP_A, EDMA_MCBSP_CHA_TX_DIR, &hMcbsp0ChTx);

	    EDMA_Mcbsp_ChannelOpen(CSL_MCBSP_A, EDMA_MCBSP_CHA_RX_DIR, &hMcbsp0ChRx);

	    EDMA_Mcbsp_ChannelOpen(CSL_MCBSP_B, EDMA_MCBSP_CHA_TX_DIR, &hMcbsp1ChTx);
	    EDMA_Mcbsp_ChannelOpen(CSL_MCBSP_B, EDMA_MCBSP_CHA_RX_DIR, &hMcbsp1ChRx);

	    /* Initialize Data for TX and corrupt RX buffer       */
        Fill_McBSP_DataBuffer_Multichannel((Uint8 *)xmtBuff0,(Uint8 *)rcvBuff0, 4*NUM_XMT_ELEMENTS);
        Fill_McBSP_DataBuffer_Multichannel((Uint8 *)xmtBuff1,(Uint8 *)rcvBuff1, 4*NUM_XMT_ELEMENTS);

	    /*Since there is only DXR or DRR register to write/read WNUMDMA/RNUMDMA =1 */

	  //  no_of_xmt_elements      = 128;
	//    no_of_receive_elements  = 128;

	    switch(j)
	    {
	    case(0):
	    	{
	    	myfifo.WriteFifoEnable	= 0;
	        myfifo.ReadFifoEnable	= 0;
	        no_of_elements = 512; //total no. of bytes of transfer
	        acnt = 4;
	        bcnt = (no_of_elements/acnt);
	        srcBIDX = acnt;
	        dstBIDX = 0;

	        break;
	        }
	    case(1):
	    	{
	    	myfifo.WriteFifoEnable	= 1;
	    	myfifo.ReadFifoEnable	= 1;
	    	myfifo.TEST_WNUMEVT     = 32;
	    	myfifo.TEST_RNUMEVT	    = 32;
	    	myfifo.TEST_WNUMDMA	    = 1;
	    	myfifo.TEST_RNUMDMA	    = 1;

	    	no_of_elements = 512; //total no. of bytes of transfer
	    	acnt = (myfifo.TEST_WNUMEVT *4);
	    	bcnt = no_of_elements/acnt;
	    	srcBIDX = acnt;
	    	dstBIDX = acnt;

	        break;
	    	}
	    default:
	        	break;
	        }


	    if(myfifo.WriteFifoEnable ==1 || myfifo.ReadFifoEnable ==1)
	        {
	        	 MCBSP0_BASE_ADDRESS= 0x22000000;
	        	 MCBSP1_BASE_ADDRESS= 0x22400000;

	        	 writeAddress0 = (Uint32 *)(MCBSP0_BASE_ADDRESS + 0x00000004); //DXR offset for the DMA path is 0x04
	        	 readAddress0  = (Uint32 *)(MCBSP0_BASE_ADDRESS + 0x00000000); //DRR offset for the DMA path is 0x00
	        	 writeAddress1 = (Uint32 *)(MCBSP1_BASE_ADDRESS + 0x00000004);
	        	 readAddress1  = (Uint32 *)(MCBSP1_BASE_ADDRESS + 0x00000000);
	        }
	    else
	        {
	        	 MCBSP0_BASE_ADDRESS= 0x021B4000;
	        	 MCBSP1_BASE_ADDRESS= 0x021B8000;

	        	 writeAddress0 = (Uint32 *)(MCBSP0_BASE_ADDRESS + 0x00000004); //DXR offset for the CPU path is 0x04
	        	 readAddress0  = (Uint32 *)(MCBSP0_BASE_ADDRESS + 0x00000000); //DRR offset for the CPU path is 0x00
	        	 writeAddress1 = (Uint32 *)(MCBSP1_BASE_ADDRESS + 0x00000004);
	             readAddress1  = (Uint32 *)(MCBSP1_BASE_ADDRESS + 0x00000000);
	        }


	     /* Enable the events on the EDMA*/


	    intrEn[0] = (1 << (Xfr_Complete_Code_Mcbsp_Tx[0]));
	    CSL_edma3HwChannelControl(hMcbsp0ChTx, CSL_EDMA3_CMD_CHANNEL_ENABLE, intrEn);
	    intrEn[0] = (1 << (Xfr_Complete_Code_Mcbsp_Rx[0]));
	    CSL_edma3HwChannelControl(hMcbsp0ChRx, CSL_EDMA3_CMD_CHANNEL_ENABLE, intrEn);
	    intrEn[0] = (1 << (Xfr_Complete_Code_Mcbsp_Tx[1]));
	    CSL_edma3HwChannelControl(hMcbsp1ChTx, CSL_EDMA3_CMD_CHANNEL_ENABLE, intrEn);
	    intrEn[0] = (1 << (Xfr_Complete_Code_Mcbsp_Rx[1]));
	    CSL_edma3HwChannelControl(hMcbsp1ChRx, CSL_EDMA3_CMD_CHANNEL_ENABLE, intrEn);

	    temp_TCC_Tx[0] =  (Xfr_Complete_Code_Mcbsp_Tx[0]-32);
	    temp_TCC_Tx[1] =  (Xfr_Complete_Code_Mcbsp_Tx[1]-32);
	    temp_TCC_Rx[0] =  (Xfr_Complete_Code_Mcbsp_Rx[0]-32);
	    temp_TCC_Rx[1] =  (Xfr_Complete_Code_Mcbsp_Rx[1]-32);

        ipr.region= CSL_EDMA3_REGION_GLOBAL;
        ipr.intrh = (1 << temp_TCC_Tx[0])|(1 << temp_TCC_Tx[1])|
                    (1 << temp_TCC_Rx[0])|(1 << temp_TCC_Rx[1]);

	    CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,&ipr);

	   xmtBuff0_global = (Uint32 *) global_address((Uint32)xmtBuff0);
	   rcvBuff0_global = (Uint32 *) global_address((Uint32)rcvBuff0);
	   xmtBuff1_global = (Uint32 *) global_address((Uint32)xmtBuff1);
	   rcvBuff1_global = (Uint32 *) global_address((Uint32)rcvBuff1);

	   // Wait for interrupt
       ipr.region  = CSL_EDMA3_REGION_GLOBAL;
       ipr.intr    = 0;
       ipr.intrh   = 0;

	    /* Iteration number varies from 0 to CLKGDV_START_VALUE */
//       for(i = 0; i <MAX_ITERATIONS; i++)
        for(i = 3; i <MAX_ITERATIONS; i++)
	    {
	        VAL_TRACE(0xcace1100 + i);

	        /* Reset the MCBSP Channel  */
	        CSL_mcbspHwControl (hMcbsp[0], CSL_MCBSP_CMD_RESET, 0);
	        CSL_mcbspHwControl (hMcbsp[1], CSL_MCBSP_CMD_RESET, 0);

	        /* configure for 128 channel mode*/
	        Configure_MultiChannel(CSL_MCBSP_A, xmt_channels, rcv_channels);
	        Configure_MultiChannel(CSL_MCBSP_B, xmt_channels, rcv_channels);

	        MCBSP_HwSetupStructFill(Mcbsp_Div[i]); /* Populate the McBSP parameters into local structure */

	        /* Fill RX buffer for both the McBSP's with zeroes */
	        Corrupt_McBSP_DataBuffer(rcvBuff0, NUM_RCV_ELEMENTS);
	        Corrupt_McBSP_DataBuffer(rcvBuff1, NUM_RCV_ELEMENTS);

	        CSL_mcbspHwSetup(hMcbsp[0], &mySetup); /* Configure the Mcbsp registers */
	        CSL_mcbspHwSetup(hMcbsp[1], &mySetup);

	        // enable Frame Sync and Sample-Rate Generator.
            *(int *)(0x21b4008) |= 0x00C00000;
            *(int *)(0x21b8008) |= 0x00C00000;

	        Edma_Mcbsp_Setup (CSL_MCBSP_A,           /*      Setup the EMDA for McBSP0              */
	        		          readAddress0,
	        		          writeAddress0,
	                          &hMcbsp0ChTx,
	                          &hMcbsp0ChRx,
	                          &hParamMcbsp0Tx,
	                          &hParamMcbsp0Rx,
	                          xmtBuff0_global,
	                          rcvBuff0_global,
	                          Xfr_Complete_Code_Mcbsp_Tx[0],
	                          Xfr_Complete_Code_Mcbsp_Rx[0],
	                          acnt,
	                          bcnt,
	                          srcBIDX,
	                          dstBIDX);

	        Edma_Mcbsp_Setup (CSL_MCBSP_B,            /*      Setup the EMDA for McBSP1              */
	        				  readAddress1,
	        		          writeAddress1,
	                          &hMcbsp1ChTx,
	                          &hMcbsp1ChRx,
	                          &hParamMcbsp1Tx,
	                          &hParamMcbsp1Rx,
	                          xmtBuff1_global,
	                          rcvBuff1_global,
	                          Xfr_Complete_Code_Mcbsp_Tx[1],
	                          Xfr_Complete_Code_Mcbsp_Rx[1],
	                          acnt,
	                          bcnt,
	                          srcBIDX,
	                          dstBIDX);


	        /*Initialize the FIFO*/
	        InitBfifo_0(myfifo.TEST_WNUMDMA, myfifo.TEST_WNUMEVT, myfifo.TEST_RNUMDMA, myfifo.TEST_RNUMEVT);
	        InitBfifo_1(myfifo.TEST_WNUMDMA, myfifo.TEST_WNUMEVT, myfifo.TEST_RNUMDMA, myfifo.TEST_RNUMEVT);

	        VAL_TRACE(0x98989898);

            for(k=0; k <= 50; k++); //adding delay

	        Tx_Rx_Clkgen_Frmgen(hMcbsp[0], MCBSP_ENABLE);   /*Enable TX, RX, SRGR clock and SRGR Frame generation */
	        Tx_Rx_Clkgen_Frmgen(hMcbsp[1], MCBSP_ENABLE);

	        VAL_TRACE(0x99990000);

	        do
	                  {
	                      CSL_edma3GetHwStatus(hModule,
	                  		        CSL_EDMA3_QUERY_INTRPEND,
	                  		        &ipr);
	                  }while(ipr.intrh!= 0x000000F0);

	                      if(ipr.intrh & (1 << temp_TCC_Tx[0]))
	                      {
	                          Mcbsp0_Tx_Edma_Done = 1;
	                          VAL_TRACE(0xedcb0000 + temp_TCC_Tx[0]);
	                      }
	                      if(ipr.intrh & (1 << temp_TCC_Tx[1]))
	                      {
	                          Mcbsp1_Tx_Edma_Done = 1;
	                          VAL_TRACE(0xedcb1000 + temp_TCC_Tx[1]);

	                      }
	                      if(ipr.intrh & (1 << temp_TCC_Rx[0]))
	                      {
	                          Mcbsp0_Rcv_Edma_Done = 1;
	                          VAL_TRACE(0xedcb0100 + temp_TCC_Rx[0]);
	                      }
	                      if(ipr.intrh & (1 << temp_TCC_Rx[1]))
	                      {
	                          Mcbsp1_Rcv_Edma_Done = 1;
	                          VAL_TRACE(0xedcb1100 + temp_TCC_Rx[1]);
	                      }

	                      CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR,&ipr);
	               //   }while(ipr.intrh!= 0);

	                  /* Set Interrupt EVAL */
	                  ipr.intr  = 0x00000000;
	                  ipr.intrh = 0x00000000;

	edma_done = Mcbsp0_Tx_Edma_Done + Mcbsp0_Rcv_Edma_Done + Mcbsp1_Tx_Edma_Done + Mcbsp1_Rcv_Edma_Done;


		/* Disable TX, RX, SRGR clock and SRGR Frame generation */
	        Tx_Rx_Clkgen_Frmgen(hMcbsp[0], MCBSP_DISABLE);
	        Tx_Rx_Clkgen_Frmgen(hMcbsp[1], MCBSP_DISABLE);

	        VAL_TRACE(0xeeee0000 + mcbspError);

	        failFlag =0;
	        /* Data comparison for McBSP0 and McBSP1 */
	     ////   if(mcbspError == 0)
	     //   {
	            failFlag = Compare_McBSP_DataBuffer_MultiChannel(xmtBuff0,
	                                                              rcvBuff0,
	                                                              NUM_XFR_ITERATIONS,
	                                                              FRAME_LENGTH1,
	                                                              xmt_channels,
	                                                              rcv_channels,
	                                                              mytxdata.wordLength1,
	                                                              mytxdata.rjust_dxenable);

	            failFlag = (failFlag & (Compare_McBSP_DataBuffer_MultiChannel(xmtBuff1,
	                                                              rcvBuff1,
	                                                              NUM_XFR_ITERATIONS,
	                                                              FRAME_LENGTH1,
	                                                              xmt_channels,
	                                                              rcv_channels,
	                                                              mytxdata.wordLength1,
	                                                              mytxdata.rjust_dxenable)));
	        VAL_TRACE(0xAAAAABCD);

	        if (failFlag != PASS)
	           {
	               VAL_TRACE(0xDEAD0000 + i);
	               VAL_TRACE(mcbsp0_spcr);
	               VAL_TRACE(mcbsp1_spcr);
	               *(profileresultsPtr++) = i;  //Store iteration number i
	               *(profileresultsPtr++) = j;
	               VAL_TRACE(myclkset.srgClkDivide);
	               *(profileresultsPtr++) = Mcbsp_Div[i]; //Store corresponding CLKGDV value
	               *(profileresultsPtr++) = 0xDEADDEAD;
	               result = FAIL;
	           }
	           else
	           {
	               VAL_TRACE(0xABCDABCD);
	               *(profileresultsPtr++) = i;  //Store iteration number i
	               *(profileresultsPtr++) = j;
	               VAL_TRACE(myclkset.srgClkDivide);
	               *(profileresultsPtr++) = Mcbsp_Div[i]; //Store corresponding CLKGDV value
	               *(profileresultsPtr++) = 0xABCDABCD;
	               result = PASS;
	           }
	        /* Clear SEC bits corresponding to EDMA Channel numbers used by writing into SECR register.
	         This is to be repeated for every iteration */

	        CSL_edma3ClearDMASecondaryEvents(hModule,secEventLo,secEventHi);
	        CSL_edma3EventsMissedClear(hModule,missedLo, missedHi, missedQdma);


		    Mcbsp0_Tx_Edma_Done = 0; Mcbsp0_Rcv_Edma_Done = 0;
	        Mcbsp1_Tx_Edma_Done = 0; Mcbsp1_Rcv_Edma_Done = 0;

	 //       rxd_cnt0 = 0; txd_cnt0 = 0; rxd_cnt1 = 0; txd_cnt1 = 0;
	        edma_done = 0; sync_error = 0;
	    } // end... for(i = 0; (i <= (CLKGDV_START_VALUE - 1)) && (mcbspError == 0); i++)

	  }

	    /* Close the EDMA channel opened for McBSP Transmit and Recieve */
	    EDMA_Mcbsp_ChannelClose(&hMcbsp0ChTx, &hMcbsp0ChRx);
	    EDMA_Mcbsp_ChannelClose(&hMcbsp1ChTx, &hMcbsp1ChRx);

	    status = CSL_mcbspClose(hMcbsp[0]);      /* Close the McBSP Handle*/
	    status = CSL_mcbspClose(hMcbsp[1]);

	    CSL_edma3Close(hModule);                    /* Close the EDMA Module*/



	    if (result == PASS)
	    	printf("Test passed\n");
	    else
	    	printf("Test failed\n");

	  return(result);
	}



	void MCBSP_HwSetupStructFill(Uint32 ClkDiv)
	{
	    /*************************************************************************/
	        /* \brief  Configure the MCBSP with following values.
		*************************************************************************
		** \note McBSP receiver, transmitter frame sync logic and sample rate
	 	** generator are not enabled in this function. This is done because
	 	** once these are enabled, McBSP will start its operation, which might
	 	** not be required till DMA and IRQ setups, if any are done.
	 	*************************************************************************/

	        myglobal.ioEnableMode                 =    CSL_MCBSP_IOMODE_TXDIS_RXDIS;

	#ifdef TB_LOOPBACK
	        myglobal.dlbMode                      =    CSL_MCBSP_DLBMODE_OFF;
	#else
		    myglobal.dlbMode                      =    CSL_MCBSP_DLBMODE_ON;    // DLB mode
	#endif

	        myglobal.clkStopMode                  =    CSL_MCBSP_CLKSTP_DISABLE;

	        myrxdata.wordReverse 	              =    CSL_MCBSP_32BIT_REVERS_DISABLE;
	        myrxdata.numPhases 	                  =    CSL_MCBSP_PHASE_SINGLE;
	        myrxdata.wordLength1 	              =    CSL_MCBSP_WORDLEN_32;
	        myrxdata.frmLength1        	          =	   FRAME_LENGTH1;
	        myrxdata.wordLength2	              =    CSL_MCBSP_WORDLEN_8;
	        myrxdata.frmLength2  	              =    FRAME_LENGTH2;
	        myrxdata.frmSyncIgn	 	              =    CSL_MCBSP_FRMSYNC_DETECT;
	        myrxdata.compand 		              =    CSL_MCBSP_COMPAND_OFF_MSB_FIRST;
            myrxdata.dataDelay                    =    CSL_MCBSP_DATADELAY_0_BIT;
	        myrxdata.rjust_dxenable 	          =    CSL_MCBSP_RJUSTDXENA_RJUST_RZF;
	        myrxdata.intEvent 		              =    CSL_MCBSP_INTMODE_ON_SYNCERR; // RINTM of SPCR . Value is 2'b11

	        mytxdata.wordReverse 	              =    CSL_MCBSP_32BIT_REVERS_DISABLE;
	        mytxdata.numPhases 	                  =    CSL_MCBSP_PHASE_SINGLE;
	        mytxdata.wordLength1 	              =    CSL_MCBSP_WORDLEN_32;
	        mytxdata.frmLength1                   =    FRAME_LENGTH1;
	        mytxdata.wordLength2		          =    CSL_MCBSP_WORDLEN_8;
	        mytxdata.frmLength2  	              =    FRAME_LENGTH2;
	        mytxdata.frmSyncIgn	 	              =    CSL_MCBSP_FRMSYNC_DETECT;
	        mytxdata.compand 		              =    CSL_MCBSP_COMPAND_OFF_MSB_FIRST;
            mytxdata.dataDelay                    =    CSL_MCBSP_DATADELAY_0_BIT;
	        mytxdata.rjust_dxenable 	          =    CSL_MCBSP_RJUSTDXENA_RJUST_RZF;
	        mytxdata.intEvent 		              =    CSL_MCBSP_INTMODE_ON_FSYNC;    //XINTM OF SPCR.Value is 2'b10


	        myclkset.frmSyncTxMode 		          =    CSL_MCBSP_FSCLKMODE_INTERNAL; // Refers to FSXM field of PCR register
            myclkset.frmSyncRxMode                =    CSL_MCBSP_FSCLKMODE_INTERNAL;  // Refers to FSRM field of PCR register
	       // myclkset.frmSyncRxMode	              =	   CSL_MCBSP_FSCLKMODE_INTERNAL;
            myclkset.clkRxMode                    =    CSL_MCBSP_TXRXCLKMODE_INTERNAL;      // Refers to CLKRM field of PCR register
	        myclkset.clkTxMode		              =    CSL_MCBSP_TXRXCLKMODE_INTERNAL;    // Refers to CLKXM field of PCR register
            myclkset.frmSyncTxPolarity            =    CSL_MCBSP_FSPOL_ACTIVE_HIGH;         //Refers to FSXP field of PCR register
            myclkset.frmSyncRxPolarity            =    CSL_MCBSP_FSPOL_ACTIVE_HIGH;      //Refers to FSRP field of PCR register
	        myclkset.clkTxPolarity		          =    CSL_MCBSP_CLKPOL_TX_FALLING_EDGE; //Refers to CLKXP field of PCR register
	        myclkset.clkRxPolarity		          =    CSL_MCBSP_CLKPOL_RX_RISING_EDGE;  //Refers to CLKRP field of PCR register
			myclkset.srgClkDivide                 =    ClkDiv ;     					//CLKGDIV OF  SRGR

	        myclkset.srgFrmPulseWidth	          =    FRAME_PULSE_WIDTH;      //FWID OF SRGR
	        myclkset.srgFrmPeriod		          =    FRAME_PERIOD;           //FPER OF SRGR

	        //myclkset.srgInputClkMode	          =    CSL_MCBSP_SRGCLK_CLKS;  		//CLKSM OF SGRGR i.e External clock source.
	        myclkset.srgInputClkMode	          =    CSL_MCBSP_SRGCLK_CLKCPU;     //Change from external clk to CPU clock
	        myclkset.srgClkPolarity		          =    CSL_MCBSP_CLKPOL_SRG_RISING_EDGE;  //CLKSP OF SRGR


	        myclkset.srgTxFrmSyncMode	          =    CSL_MCBSP_TXFSMODE_SRG;   // FSGM OF SRGR


	        myclkset.srgClkSync		              =    CSL_MCBSP_CLKGSYNCMODE_OFF;  //GSYNC OF SRGR

            mymulCh.rxPartition                   =    CSL_MCBSP_PARTMODE_2PARTITION;  //All 128 Channels are enabled
            mymulCh.txPartition                   =    CSL_MCBSP_PARTMODE_2PARTITION;
	        mymulCh.rxMulChSel		              =    CSL_MCBSP_MULTI_CHANNEL_RX_EN_ALL; // RMCM =0 in MCR register
	        mymulCh.txMulChSel		              =    CSL_MCBSP_MULTI_CHANNEL_TX_EN_NO_MASK;  //XMCM =2'b01 in MCR reg
	        mymulCh.rxPartABlk		              =    CSL_MCBSP_PABLK_0;
	        mymulCh.rxPartBBlk		              =    CSL_MCBSP_PBBLK_1;
	        mymulCh.txPartABlk		              =    CSL_MCBSP_PABLK_0;
	        mymulCh.txPartBBlk		              =    CSL_MCBSP_PBBLK_1;
	        //mySetup.emumode			              =    CSL_MCBSP_EMU_STOP;
                mySetup.emumode                       =    CSL_MCBSP_EMU_FREERUN;

	        mySetup.global                        =    &myglobal;
	        mySetup.rxdataset                     =    &myrxdata;
	        mySetup.txdataset                     =    &mytxdata;
	        mySetup.clkset                        =    &myclkset;
	        mySetup.mulCh                         =    &mymulCh;

	}

/*
 * mcbspMasterDigLpbk.c
 *
 * This file contains the test / demo code to demonstrate the McBSP driver
 * master functionality using Digital Loopback setup. The file configures 
 * the EVM in master mode.
 *
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/

/* ========================================================================== */
/*                            INCLUDE FILES                                   */
/* ========================================================================== */

#include <ti/sysbios/BIOS.h>
#include <xdc/std.h>
#include <ti/sysbios/knl/task.h>
#include <string.h>
#include <ti/sysbios/knl/Queue.h>
#include <xdc/runtime/System.h>

#include <xdc/cfg/global.h>

/* Include EDMA3 Driver */
#include <ti/sdo/edma3/drv/edma3_drv.h>

/* CSL Chip Functional Layer */
#include <ti/csl/csl_chip.h>

/* CSL Cache Functional Layer */
#include <ti/csl/csl_cacheAux.h>

/* CSL CPINTC Include Files. */
#include<ti/csl/csl_cpIntc.h>

/* MCBSP Driver Include File. */
#include <ti/drv/mcbsp/mcbsp_drv.h>
#include <ti/drv/mcbsp/mcbsp_osal.h>

/* PlatformLib Include File */
#include <ti/platform/platform.h>


/* ========================================================================== */
/*                        EXTERNAL FUNCTIONS                                  */
/* ========================================================================== */

extern EDMA3_DRV_Handle edma3init(unsigned int edma3Id, EDMA3_DRV_Result *);

extern void McbspDevice_init(void);

extern int32_t Osal_dataBufferInitMemory(uint32_t dataBufferSize);

/* FPGA Configuration Misc-1 Register offset */
#define MCBSP_FPGA_MISC_REG_OFFSET (0x0C)

/* ========================================================================== */
/*                           MACRO DEFINTIONS                                 */
/* ========================================================================== */

#define NUM_BUFS              2             /* Max of 2 outstanding requests  */
#define NUM_OF_CHANNELS       24             /* Number of slots to be used     */
#define BUFSIZE               (80*NUM_OF_CHANNELS)          /* 1K of data transceive          */

/* Defines the core number responsible for system initialization. */
#define CORE_SYS_INIT               0

/*============================================================================*/
/*                            GLOBAL VARIABLES                                */
/*============================================================================*/

/* Shared Memory Variable to ensure synchronizing MCBSP initialization
 * with all the other cores. */
/* Created an array to pad the cache line with MCBSP_CACHE_LENGTH size */
#pragma DATA_ALIGN   (isMCBSPInitialized, MCBSP_MAX_CACHE_ALIGN)
#pragma DATA_SECTION (isMCBSPInitialized, ".mcbspSharedMem");
volatile Uint32 isMCBSPInitialized[(MCBSP_CACHE_LENGTH / sizeof(Uint32))] = { 0 };

/* Handle to the EDMA driver instance                                         */
#pragma DATA_ALIGN   (hEdma, MCBSP_MAX_CACHE_ALIGN)
EDMA3_DRV_Handle hEdma[(MCBSP_CACHE_LENGTH / sizeof(EDMA3_DRV_Handle))] = { NULL };

/* Handle to MCBSP driver instance */
typedef void* Mcbsp_DevHandle;
Mcbsp_DevHandle  hMcbspDev;

/* Handle to MCBSP driver channel instance */
typedef void* Mcbsp_ChanHandle;
Mcbsp_ChanHandle  hMcbspTxChan;
Mcbsp_ChanHandle  hMcbspRxChan;

/* Core Number Identifier */
UInt32 coreNum = 0xFFFF;

/* Array to hold the pointer to the allocated buffers     */
void* bufRx[NUM_BUFS];
void* bufTx[NUM_BUFS];

/* Variables to indicate status of EDMA TX and RX requests */
volatile uint32_t edmaTxDone = 0;
volatile uint32_t edmaRxDone = 0;
volatile uint32_t edmaTxCountDone=0;
volatile uint32_t edmaRxCountDone=0;
/**
 * \brief    Mcbsp Sample rate generator default parameters.
 *
 */
Mcbsp_srgConfig mcbspSrgCfg =
{
    FALSE,                     /* No gsync to be used as input is not CLKS    */
    Mcbsp_ClkSPol_RISING_EDGE, /* Dont care as input clock is not clks        */
    Mcbsp_SrgClk_CLKCPU,       /* McBSP internal clock to be used             */
    166666667,                 /* Mcbsp internal clock frequency(PLL-SYSCLK6) */
    0                          /* frame sync pulse width (val+1) is used      */
};

/**
 * \brief    Mcbsp device creation default parameters.
 *
 */
const Mcbsp_Params Mcbsp_PARAMS =
{
    Mcbsp_DevMode_McBSP,       /* Use the device as MCBSP                     */
    Mcbsp_OpMode_DMAINTERRUPT, /* Use DMA mode of operation                   */
    TRUE,                      /* cache coherency taken care of by driver     */
    Mcbsp_EmuMode_SOFT_STOP,   /* Soft mode is to be enabled                  */
    Mcbsp_Loopback_DISABLE,    /* Loop back mode disabled                     */
    &mcbspSrgCfg,              /* sample rate generator configuration         */
    NULL,                      /* TX pending buffer queue from application    */
    NULL,                      /* TX floating buffer queue in DMA             */
    NULL,                      /* RX pending buffer queue from application    */
    NULL                       /* RX floating buffer queue in DMA             */
};

#pragma DATA_ALIGN(loopJob, MCBSP_MAX_CACHE_ALIGN)
static Int32 loopJob[16] = {
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0
};

/**< settings to configure the TX or RX hardware sections                 */
Mcbsp_DataConfig mcbspChanConfig =
{
    Mcbsp_Phase_SINGLE,
    Mcbsp_WordLength_32,
    Mcbsp_WordLength_32,    /* Dont care for single phase*/
    NUM_OF_CHANNELS,
    NUM_OF_CHANNELS,      // Only using single phase, hence num channels is 0
    Mcbsp_FrmSync_DETECT,
    Mcbsp_DataDelay_1_BIT,
    Mcbsp_Compand_OFF_MSB_FIRST,
    Mcbsp_BitReversal_DISABLE,
    Mcbsp_IntMode_ON_SYNCERR,
    Mcbsp_RxJust_RZF,  /* Dont care for TX         */
    Mcbsp_DxEna_OFF
};

/**< clock setup for the TX section                     */
Mcbsp_ClkSetup mcbspClkConfigTx =
{
    Mcbsp_FsClkMode_INTERNAL,
    8000,                   /* 96KHz                   */
    Mcbsp_TxRxClkMode_INTERNAL,
    Mcbsp_FsPol_ACTIVE_HIGH,
    Mcbsp_ClkPol_RISING_EDGE
};

/**< clock setup for the RX section                     */
Mcbsp_ClkSetup mcbspClkConfigRx =
{
    Mcbsp_FsClkMode_EXTERNAL,
    8000,                   /* 96KHz                   */
    Mcbsp_TxRxClkMode_EXTERNAL,
    Mcbsp_FsPol_ACTIVE_HIGH,
    Mcbsp_ClkPol_FALLING_EDGE
};

/**< Multi channel setup                                                      */
Mcbsp_McrSetup mcbspMultiChanCtrl =
{
    Mcbsp_McmMode_ALL_CHAN_ENABLED_UNMASKED,
    Mcbsp_PartitionMode_CHAN_0_15,
    Mcbsp_PartitionMode_CHAN_16_31,
    Mcbsp_PartitionMode_2
};

Mcbsp_ChanParams mcbspChanparamTx =
{
    Mcbsp_WordLength_32,  /* wordlength configured    */
    &loopJob[0],          /* loop job buffer internal */
    8,                    /* user loopjob length      */
    NULL,                 /* global error callback    */
    NULL,                 /* edma Handle              */
    1,                    /* EDMA event queue         */
    8,                    /* hwi number               */
    Mcbsp_BufferFormat_MULTISLOT_NON_INTERLEAVED,
    TRUE,                 /* FIFO mode enabled        */
    &mcbspChanConfig,     /* channel configuration    */
    &mcbspClkConfigTx,    /* clock configuration      */
    &mcbspMultiChanCtrl,  /* multi channel control    */
    0x00,
    0x00,
    0x00,
    0x00
};

Mcbsp_ChanParams mcbspChanparamRx =
{
    Mcbsp_WordLength_32,  /* wordlength configured    */
    &loopJob[0],          /* loop job buffer internal */
    8,                    /* user loopjob length      */
    NULL,                 /* global error callback    */
    NULL,                 /* edma Handle              */
    2,                    /* EDMA event queue         */
    8,                    /* hwi number               */
    Mcbsp_BufferFormat_MULTISLOT_NON_INTERLEAVED,
    TRUE,                 /* FIFO mode enabled        */
    &mcbspChanConfig,     /* channel configuration    */
    &mcbspClkConfigRx,    /* clock configuration      */
    &mcbspMultiChanCtrl,  /* multi channel control    */
    0x00,
    0x00,
    0x00,
    0x00
};


/* ========================================================================== */
/*                           FUNCTION DEFINITIONS                             */
/* ========================================================================== */

/*
 *   This is the application's callback function. The driver will
 *   call this function whenever an EDMA I/O operation is over.
 *
 */
void mcbspAppCallback(void* arg, Mcbsp_IOBuf *ioBuf)
{
	  int32_t mode;
    int32_t *pmode = (int32_t *)arg;

    mode = *pmode;
    if (mode == MCBSP_MODE_OUTPUT)
    {
        edmaTxDone = 1;
        edmaTxCountDone++;
    }
    else if (mode == MCBSP_MODE_INPUT)
    {
        edmaRxDone = 1;
        edmaRxCountDone++;
    }
    return;
}

void testMcBSPLoop(void);

/*
 * \brief   This function demostrates the use of Mcbsp using digital loopback
 *          communication setup.
 *
 * \param   None
 *
 * \return  None
 */
void mcbspDigLpbkApp(UArg arg0, UArg arg1)
{
    /**< Mcbsp device params                                                  */
    Mcbsp_Params  mcbspParams;
    /**< Mcbsp sample rate configuration parameters                           */
    Mcbsp_srgConfig  mcbspSrgParams;

    /**< Queue to hold the pending packets received from the application      */
    Queue_Struct  txQueuePendingList, rxQueuePendingList;
    /**< Queue to manage floating packets in DMA                              */
    Queue_Struct  txQueueFloatingList, rxQueueFloatingList;

    uint32_t count   = 0, tempCount = 0;
    int32_t  status  = 0, retval = 0;
    int32_t  txChanMode = MCBSP_MODE_OUTPUT;
    int32_t  rxChanMode = MCBSP_MODE_INPUT;
    uint32_t mcbspTxDone = 0, mcbspRxDone = 0;
    Mcbsp_IOBuf txFrame, rxFrame;

    /* Initialize the OSAL */
    if (Osal_dataBufferInitMemory(BUFSIZE) < 0)
    {
	    System_printf ("Debug(Core %d): Error: Unable to initialize the OSAL. \n", coreNum);
	    return;
    }

    /* update EDMA3 handle to channel parameters */
    mcbspChanparamTx.edmaHandle = hEdma[0];
    mcbspChanparamRx.edmaHandle = hEdma[0];

    /* create the pending and floating queue for the TX channel           */
    Queue_construct(&txQueuePendingList, NULL);
    Queue_construct(&txQueueFloatingList, NULL);

    /* create the pending and floating queue for the RX channel           */
    Queue_construct(&rxQueuePendingList, NULL);
    Queue_construct(&rxQueueFloatingList, NULL);

    /* configure the SRG properties                                           */
    /* use Mcbsp intenal clock      */
    mcbspSrgParams.srgInputClkMode = Mcbsp_SrgClk_CLKCPU;
    /* 1 bit width framesync        */
    mcbspSrgParams.srgFrmPulseWidth = 0;
    /* internal clock frequncy      */
    mcbspSrgParams.srgrInputFreq = 166666667; /* 166.67 MHz - SYSCLK6 */

    mcbspParams                 = Mcbsp_PARAMS;
    mcbspParams.mode            = Mcbsp_DevMode_McBSP;
    mcbspParams.opMode          = Mcbsp_OpMode_DMAINTERRUPT;
    mcbspParams.enablecache     = TRUE;
    mcbspParams.emulationMode   = Mcbsp_EmuMode_FREE;
    mcbspParams.dlbMode         = Mcbsp_Loopback_ENABLE;//Mcbsp_Loopback_DISABLE;
    mcbspParams.srgSetup        = &mcbspSrgParams;
    mcbspParams.txQPendingList  = &txQueuePendingList;
    mcbspParams.txQFloatingList = &txQueueFloatingList;
    mcbspParams.rxQPendingList  = &rxQueuePendingList;
    mcbspParams.rxQFloatingList = &rxQueueFloatingList;

    /* Bind the driver instance with device instance */
    status = mcbspBindDev(&hMcbspDev, coreNum, &mcbspParams);

    if (status != MCBSP_STATUS_COMPLETED)
    {
        System_printf ("Debug(Core %d): MCBSP LLD Bind Device Failed\n", coreNum);
        return;
    }

    /* Create a RX channel for receiving */
    status = mcbspCreateChan(&hMcbspRxChan, hMcbspDev, MCBSP_MODE_INPUT, &mcbspChanparamRx, mcbspAppCallback, &rxChanMode);
    if (MCBSP_STATUS_COMPLETED != status)
    {
        System_printf ("Debug(Core %d): Error: Create Channel (RX) failed\n", coreNum);
        return;
    }

    /* Create a TX channel for the transmission */
    status = mcbspCreateChan(&hMcbspTxChan, hMcbspDev, MCBSP_MODE_OUTPUT, &mcbspChanparamTx, mcbspAppCallback, &txChanMode);
    if (MCBSP_STATUS_COMPLETED != status)
    {
        System_printf ("Debug(Core %d): Error: Create Channel (TX) failed\n", coreNum);
        return;
    }

    /* create the buffers required for the TX and RX operations */
    for (count = 0; count < (NUM_BUFS); count++)
    {
        bufTx[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE);
        bufRx[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE);

        if (bufTx[count] == NULL)
        {
            System_printf ("Debug(Core %d): Error: Tx Buffer (%d) Memory Allocation Failed\n", coreNum, count);
            return;
        }
        if (bufRx[count] == NULL)
        {
            System_printf ("Debug(Core %d): Error: Rx Buffer (%d) Memory Allocation Failed\n", coreNum, count);
            return;
        }
    }

    /* Fill the buffers with known data and transmit the same and 
       check if the same pattern is received */
    for (count = 0; count < (NUM_BUFS); count++)
    {
        memset((uint8_t *)bufTx[count], 0, BUFSIZE);
        for (tempCount = 0; tempCount < BUFSIZE; tempCount++)
        {
            ((uint8_t *)bufTx[count])[tempCount] = (tempCount % 0x100);
        }
    }
    testMcBSPLoop();
}

int edmaSuccessCnt=0;
int edmaDebug=1;
int mcbspRxBufEdmaIndex = 0;
int mcbspRxBufRdIndex = 1;
int mcbspTxBufEdmaIndex = 0;
int mcbspTxBufWrIndex = 1;

void testMcBSPLoop(void)
{
    uint32_t count   = 0, tempCount = 0, newcount=0;
    int32_t  status  = 0, retval = 0;
    int32_t  txChanMode = MCBSP_MODE_OUTPUT;
    int32_t  rxChanMode = MCBSP_MODE_INPUT;
    uint32_t mcbspTxDone = 0, mcbspRxDone = 0;
    Mcbsp_IOBuf txFrame, rxFrame;
    newcount=0;
#if 1
    newcount++;
	count = newcount & 1;

	mcbspRxBufEdmaIndex = (mcbspRxBufEdmaIndex +1)%NUM_BUFS;
	mcbspRxBufRdIndex = (mcbspRxBufRdIndex +1)%NUM_BUFS;
	mcbspTxBufEdmaIndex = (mcbspTxBufEdmaIndex +1)%NUM_BUFS;
	mcbspTxBufWrIndex = (mcbspTxBufWrIndex +1)%NUM_BUFS;
    memset((uint8_t *)bufRx[mcbspRxBufEdmaIndex], 0, BUFSIZE);

    /* RX frame processing */
    rxFrame.cmd = Mcbsp_IOBuf_Cmd_READ;
    rxFrame.addr = (void*)bufRx[mcbspRxBufEdmaIndex];
    rxFrame.size = BUFSIZE;
    rxFrame.arg = (uint32_t) hMcbspRxChan;
    rxFrame.status = MCBSP_STATUS_COMPLETED;
    rxFrame.misc = 1;   /* reserved - used in callback to indicate asynch packet */

    status = mcbspSubmitChan(hMcbspRxChan, (void *)&rxFrame);
    if (status != MCBSP_STATUS_PENDING)
    {
        System_printf ("Debug(Core %d): Error: RX buffer submission in iteration-%d FAILED\n", coreNum, newcount);
        retval = 1;
    }
    else
    {
        //System_printf ("Debug(Core %d): RX buffer in iteration-%d is submitted to MCBSP driver\n", coreNum, newcount);
    }

    /* TX frame processing */
    txFrame.cmd = Mcbsp_IOBuf_Cmd_WRITE;
    txFrame.addr = (void*)bufTx[mcbspTxBufEdmaIndex];
    txFrame.size = BUFSIZE;
    txFrame.arg = (uint32_t)hMcbspTxChan;
    txFrame.status = MCBSP_STATUS_COMPLETED;
    txFrame.misc = 1;   /* reserved - used in callback to indicate asynch packet */

    status = mcbspSubmitChan(hMcbspTxChan, (void *)&txFrame);
    if (status != MCBSP_STATUS_PENDING)
    {
        System_printf ("Debug(Core %d): Error: TX frames submission in iteration-%d FAILED\n", coreNum, newcount);
        retval = 1;
    }
    else
    {
        //System_printf ("Debug(Core %d): TX frames in iteration-%d are submitted to MCBSP driver\n", coreNum, newcount);
    }
#endif
    /* submit frames to the driver */
    while(1)
    {
        /* Wait for TX and RX processing to complete */
		retval = 0;
        while (1)
        {
        	Task_sleep(1);
            if (edmaTxDone == 1)
            {
                //System_printf ("Debug(Core %d): EDMA -> Iteration-%d frames are transmitted to TX path\n", coreNum, newcount);
                edmaTxDone = 0; /* Reset for next iteration */
                mcbspTxDone = 1;
            }
            if (edmaRxDone == 1)
            {
                //System_printf ("Debug(Core %d): EDMA -> Iteration-%d frames are received from RX path\n", coreNum, newcount);
                edmaRxDone = 0;  /* Reset for next iteration */
                mcbspRxDone = 1;
            }
            if ((mcbspTxDone == 1) && (mcbspRxDone == 1))
            {
                mcbspTxDone = 0;  /* Reset for next iteration */
                mcbspRxDone = 0;  /* Reset for next iteration */
                break;
            }
        }
    	newcount++;
    	count = newcount & 1;

    	mcbspRxBufEdmaIndex = (mcbspRxBufEdmaIndex +1)%NUM_BUFS;
    	mcbspRxBufRdIndex = (mcbspRxBufRdIndex +1)%NUM_BUFS;
    	mcbspTxBufEdmaIndex = (mcbspTxBufEdmaIndex +1)%NUM_BUFS;
    	mcbspTxBufWrIndex = (mcbspTxBufWrIndex +1)%NUM_BUFS;

        memset((uint8_t *)bufRx[mcbspRxBufEdmaIndex], 0, BUFSIZE);

        /* RX frame processing */
        rxFrame.cmd = Mcbsp_IOBuf_Cmd_READ;
        rxFrame.addr = (void*)bufRx[mcbspRxBufEdmaIndex];
        rxFrame.size = BUFSIZE;
        rxFrame.arg = (uint32_t) hMcbspRxChan;
        rxFrame.status = MCBSP_STATUS_COMPLETED;
        rxFrame.misc = 1;   /* reserved - used in callback to indicate asynch packet */

        status = mcbspSubmitChan(hMcbspRxChan, (void *)&rxFrame);
        if (status != MCBSP_STATUS_PENDING)
        {
            System_printf ("Debug(Core %d): Error: RX buffer submission in iteration-%d FAILED\n", coreNum, newcount);
            retval = 1;
        }
        else
        {
            //System_printf ("Debug(Core %d): RX buffer in iteration-%d is submitted to MCBSP driver\n", coreNum, newcount);
        }

        /* TX frame processing */
        txFrame.cmd = Mcbsp_IOBuf_Cmd_WRITE;
        txFrame.addr = (void*)bufTx[mcbspTxBufEdmaIndex];
        txFrame.size = BUFSIZE;
        txFrame.arg = (uint32_t)hMcbspTxChan;
        txFrame.status = MCBSP_STATUS_COMPLETED;
        txFrame.misc = 1;   /* reserved - used in callback to indicate asynch packet */

        status = mcbspSubmitChan(hMcbspTxChan, (void *)&txFrame);
        if (status != MCBSP_STATUS_PENDING)
        {
            System_printf ("Debug(Core %d): Error: TX frames submission in iteration-%d FAILED\n", coreNum, newcount);
            retval = 1;
        }
        else
        {
            //System_printf ("Debug(Core %d): TX frames in iteration-%d are submitted to MCBSP driver\n", coreNum, newcount);
        }
        /* compare buffer contents */
        if(edmaDebug)
        {
        	for (tempCount = 0; tempCount < BUFSIZE; tempCount++)
        	{
        		if (((char *)bufTx[mcbspTxBufWrIndex])[tempCount] != ((char *)bufRx[mcbspRxBufRdIndex])[tempCount])
        		{
        			System_printf("Debug(Core %d): Error: TX and RX frame data DOES NOT match in iteration-%d\n",
        				coreNum, count);
        			System_printf("Debug(Core %d): Error: Buffer index = %d, Tx data = %d, Rx data = %d\n", coreNum,
                        tempCount, ((char *)bufTx[count])[tempCount], ((char *)bufRx[count])[tempCount]);
        			retval = 1;
        			break;
        		}
        	}
        	if (tempCount >= BUFSIZE)
        	{
        		edmaSuccessCnt++;
        		if(edmaDebug) System_printf("Debug(Core %d): TX and RX frames data match in iteration-%d !!![%d, %d, %d, %d]\n", coreNum, newcount,mcbspRxBufEdmaIndex, mcbspRxBufRdIndex, mcbspTxBufEdmaIndex, mcbspTxBufWrIndex);
        	}

        	if (retval == 0)
        	{
        		//System_printf("Debug(Core %d): MCBSP Digital Loopback Application completed successfully !!!\n", coreNum);
        	}
        	else
        	{
        		System_printf("Debug(Core %d): MCBSP Digital Loopback application FAILED !!!\n", coreNum);
        		retval = 0;/* For Debugging */
        	}
        }
    }


    return;
}

/*
 * \brief  Void main(Void)
 *
 *         Main function of the sample application. This function calls the
 *         function to configure the mcbsp instance.
 *
 * \param  None
 *
 * \return None
 */
Void myStartupFxn(Void)
{

	//BIOS_start();
}
Void mcbspmain0(Void);
Void main(void)
{
	mcbspmain0();
}
Void mcbspmain0(Void)
{
    Task_Params taskParams;
    EDMA3_DRV_Result edmaResult = 0;
    uint8_t uchValue;

    /* Get the core number. */
    coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);

#ifdef SIMULATOR_SUPPORT
#warn MCBSP Digital Loopback example is not supported on SIMULATOR !!!
    System_printf ("MCBSP Digital Loopback example is not supported on SIMULATOR. Exiting!\n");
    return;
#else
    System_printf ("Debug(Core %d): Running MCBSP Digital Loopback example on the DEVICE\n", coreNum);
#endif

    /* Initialize the system only if the core was configured to do so. */
    if (coreNum == CORE_SYS_INIT)
    {
        System_printf ("Debug(Core %d): System Initialization for MCBSP\n", coreNum);

        /* Drive McBSP_AMC_EN# high. Output SLCLKs, TxCLKs, RxCLKs, FSTs, FSRs as Hi-Z. 
         * These clocks and syncs are tri-stated and McBSP is accessed over 80-pin header */
        if (0 != (platform_fpgaWriteConfigReg(MCBSP_FPGA_MISC_REG_OFFSET, 11)))
        {
            System_printf ("Debug(Core %d): FPGA McBSP_AMC_EN# register WRITE failed \n", coreNum);
            return;
        }
        /* DEBUG: Verify if FPGA register is configured correctly */
        if (0 != (platform_fpgaReadConfigReg(MCBSP_FPGA_MISC_REG_OFFSET, &uchValue)))
        {
            System_printf ("Debug(Core %d): FPGA McBSP_AMC_EN# register READ failed \n", coreNum);
            return;
        }
        if (11 != uchValue)
        {
            System_printf ("Debug(Core %d): FPGA McBSP_AMC_EN# register setting failed \n", coreNum);
            return;
        }
        else
        {
            System_printf ("Debug(Core %d): FPGA McBSP_AMC_EN# register is set to %d \n", coreNum, uchValue);
        }

        /* MCBSP Driver Initialization: This should always be called before
         * invoking the MCBSP Driver. */
        mcbspInit();

        /* Device Specific MCBSP Initializations */
        McbspDevice_init();
        
        /* MCBSP Driver is operational at this time. */
        System_printf ("Debug(Core %d): MCBSP Driver Initialization Done\n", coreNum);

        /* Write to the SHARED memory location at this point in time. The other cores cannot execute
         * till the MCBSP Driver is up and running. */
        isMCBSPInitialized[0] = 1;

        /* The MCBSP IP block has been initialized. We need to writeback the cache here because it will
         * ensure that the rest of the cores which are waiting for MCBSP to be initialized would now be
         * woken up. */
        CACHE_wbL1d ((void *) &isMCBSPInitialized[0], MCBSP_MAX_CACHE_ALIGN, CACHE_FENCE_WAIT);
    }
    else
    {
        /* All other cores need to wait for the MCBSP to be initialized before they proceed with the test. */ 
        System_printf ("Debug(Core %d): Waiting for MCBSP to be initialized.\n", coreNum);

        /* All other cores loop around forever till the MCBSP is up and running. 
         * We need to invalidate the cache so that we always read this from the memory. */
        while (isMCBSPInitialized[0] == 0)
            CACHE_invL1d ((void *) &isMCBSPInitialized[0], MCBSP_MAX_CACHE_ALIGN, CACHE_FENCE_WAIT);

        System_printf ("Debug(Core %d): MCBSP can now be used.\n", coreNum);
    }

    /* Initialize EDMA3 library */
    hEdma[0] = edma3init(0, &edmaResult);

    if (edmaResult != EDMA3_DRV_SOK)
    {
      /* Report EDMA Error */
      System_printf("Debug(Core %d): EDMA Driver Initialization FAILED\n", coreNum);
    }
    else
    {
      System_printf("Debug(Core %d): EDMA Driver Initialization Done\n", coreNum);
    }

    /* Create the Digital Loopback Application Task */
    Task_Params_init(&taskParams);
    Task_create(mcbspDigLpbkApp, &taskParams, NULL);

    /* Start BIOS */
    BIOS_start();

    return;
}

/* ========================================================================== */
/*                                END OF FILE                                 */
/* ========================================================================== */