Not all enabled MSI Interrupts triggering ISR

Carey B

Other Parts Discussed in Thread: TMS320C6671

I am testing my code for MSI interrupts using a TMS320C6678EVM board operating as an RC running CCS 5.1.0. I have no EP, but think I should be able to trigger the MSI interrupts to verify my code without one. I am triggering the MSI interrupts both by writing to the MSI IRQ register in directly or writing to the appropriate raw register using Memory Browser. I have enabled several interrupts on all 8 enable registers and can see they are enabled using the memory browser on the that memory (starting at 0x21800054). When I trigger 0, 8, 16 or 24 (all in MSI0), the ISR gets called, any other single interrupt, and the ISR does not get called, even though the interrupts are enabled.

over 13 years ago

0 Steven Connell over 13 years ago

TI__Mastermind 45025 points

Hi Carey B,

Which version of SYS/BIOS are you using?

Are you having a problem with SYS/BIOS?

Steve

0 Carey B over 13 years ago in reply to Steven Connell

Prodigy 50 points

SYS/BIOS 6.33.4.39.

It's not really a problem with the SYS/BIOS

0 Carey B over 13 years ago in reply to Steven Connell

Prodigy 50 points

Here is some additional information with screenshots of the memory browser during these tests. Perhaps it's because we don't have an EP configured.

8780.MSI Example.pdf

0 Steven Connell over 13 years ago in reply to Carey B

TI__Mastermind 45025 points

I think you may be better served in a different forum, so I'll ask that your thread get moved.

In the meantime, I found this when I googled about your issue and thought it may help you:

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/199151.aspx

Steve

0 Steven Ji over 13 years ago

TI__Genius 12065 points

Carey,

Are you only using Core0 for your testing please?

Please take a look at the footnote #4 in C66x CorePac Primary Interrupts table (Table 7-38) in the C6678 data manual: CorePac[n] will receive PCIEXpress_MSI_INTn.

So CorePac 0 will only receive interrupt from MSI_0 (vectors 0/8/16/24). Similarly, Core1 will receive MSI_1 (vectors 1/9/17/25), Core 7 will receive MSI_7, etc.

Hope it helps.

0 Carey B over 13 years ago in reply to Steven Ji

Prodigy 50 points

Yes, we are only using Core0 for this test. Thank you, you solved the issue and now I understand why I was having this trouble.

However, please tell me, on the single core (TMS320C6671), which says the exact same thing in the Data Manual and is the same multi-core architecture DSP, but with a single core, does this mean that only MSI0 can be used for the single core DSP? This would limit the TMS320C6671 to 4 MSI interrupts.

0 Steven Ji over 13 years ago in reply to Carey B

TI__Genius 12065 points

Carey,

You are right that on C6671 only MSI0 is connected to CorePac0 and only those 4 MSI interrupt vectors in MSI0 are able to trigger the CorePac interrupt.

Hope it is still fine for your application using the single core device.

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Not all enabled MSI Interrupts triggering ISR