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DM3730 SPI problem

Other Parts Discussed in Thread: DM3730, SYSCONFIG
Hi,

 

I am developing a simple SPI driver in Linux for DM3730. DM3730 is master and the slaves are all digital potmeters so the communication is simple one-way one-byte transfers. I have followed the steps in DM37x Tech Ref manual to the best of my knowledge, but I cannot get any output on the SPI1 Pins. I have tried configuring the pins as GPIO and then I can toggle them, so I am sure that I am looking at the right pins.

 

SPI1 Pins are configured to muxmode 0 (CONTROL_PADCONF_MCSPI1_CLK = 0x01100110)
SPI1 functional and interface clocks are enabled

 

I have used "20.6.2.6.1 McSPI Initialization Sequence" and "20.6.2.6.2 Operations for the First Slave (On Channel 0)" for writing my code.
Here is my init code and transfer function:

 

void HAL_spi1Init(void)
{
    void __iomem *regist = NULL;
    u32 reg4 = 0;

 

    dbg_print("");

 

    regist = ioremap(CM_ICLKEN1_CORE, 4);
    reg4 = __raw_readl(regist);
    __raw_writel(reg4 | (1<<EN_MCSPI1), regist);

 

    regist = ioremap(CM_FCLKEN1_CORE, 4);
    reg4 = __raw_readl(regist);
    __raw_writel(reg4 | (1<<EN_MCSPI1), regist);

 

    regist = ioremap(MCSPI1_BASE + MCSPI_SYSCONFIG, 4);
    reg4 = (1<<MCSPI_SOFTRESET);
    __raw_writel(reg4, regist);

 

    regist = ioremap(MCSPI1_BASE + MCSPI_SYSSTATUS, 4);
    while (__raw_readl(regist)!=1) {}

 

    regist = ioremap(MCSPI1_BASE + MCSPI_CHxCONF, 4);
    reg4 = (1<<MCSPI_DPE0) | (0x07<<MCSPI_WL) | (1<<MCSPI_EPOL) | (2<<MCSPI_CLKD);
    __raw_writel(reg4, regist);

 

    regist = ioremap(MCSPI1_BASE + MCSPI_MODULCTRL, 4);
    reg4 = (1<<MCSPI_SINGLE);
    __raw_writel(reg4, regist);

   

    regist = ioremap(MCSPI1_BASE + MCSPI_SYST, 4);
    reg4 = (1<<MCSPI_SPIDATDIR0);
    __raw_writel(reg4, regist);
}
void spi1StartTransfer(u8 slave, u8 channel)
{
    void __iomem *SPI1_CH0_CTRL = ioremap(MCSPI1_BASE + MCSPI_CHxCTRL, 4);
    u32 reg = 0;

 

    reg = __raw_readl(SPI1_CH0_CTRL);
    __raw_writel(reg | (1<<MCSPI_EN), SPI1_CH0_CTRL);
    HAL_GPIO_CS(slave, channel, ENABLE_CS);
}

 

void spi1EndTransfer(u8 slave, u8 channel)
{
    void __iomem *SPI1_CH0_CTRL = ioremap(MCSPI1_BASE + MCSPI_CHxCTRL, 4);
    u32 reg = 0;

 

    reg = __raw_readl(SPI1_CH0_CTRL);
    __raw_writel(reg & ~(1<<MCSPI_EN), SPI1_CH0_CTRL);
    HAL_GPIO_CS(slave, channel, DISABLE_CS);
}

 

void HAL_spi1TransferByte(u8 data, u8 channel, u8 slave)
{
    void __iomem *SPI1_CH0_TX = ioremap(MCSPI1_BASE + MCSPI_TXx, 4);
    void __iomem *SPI1_CH0_STAT = ioremap(MCSPI1_BASE + MCSPI_CHxSTAT, 4);
    void __iomem *SPI1_IRQSTATUS = ioremap(MCSPI1_BASE + MCSPI_IRQSTATUS, 4);
    u32 reg = 0;

 

    dbg_print("");
    spi1StartTransfer(slave, channel);

 

HAL_spi1PrintRegisters();

 

    reg = __raw_readl(SPI1_IRQSTATUS);
    __raw_writel(reg | (1<<MCSPI_TX0_EMPTY),SPI1_IRQSTATUS);

 

    __raw_writel((u32) data, SPI1_CH0_TX);

 

    if ((__raw_readl(SPI1_IRQSTATUS)&(1<<MCSPI_TX0_EMPTY))!=0) {
        dbg_print("Retrying write to TX");
        reg = __raw_readl(SPI1_IRQSTATUS);
        __raw_writel(reg | (1<<MCSPI_TX0_EMPTY),SPI1_IRQSTATUS);

       

        __raw_writel((u32) data, SPI1_CH0_TX);
        if ((__raw_readl(SPI1_IRQSTATUS)&(1<<MCSPI_TX0_EMPTY))!=0) {
            dbg_print("Aborting transfer");
            return;
        }
        else {
            dbg_print("2nd write to TX successfull");
        }
    }
    else {
        dbg_print("Write to TX successfull");
    }

 

HAL_spi1PrintRegisters();

 

    spi1EndTransfer(slave, channel);
}

 

The debug output shows that the write to TX is successfull and the registers are the same before and after the write:
MCSPI_REVISION : 0x00000021
MCSPI_SYSCONFIG : 0x00000015
MCSPI_SYSSTATUS : 0x00000001
MCSPI_IRQSTATUS : 0x00000000
MCSPI_IRQENABLE : 0x00000000
MCSPI_WAKEUPENABLE : 0x00000001
MCSPI_SYST : 0x00000100
MCSPI_MODULCTRL : 0x00000001
MCSPI_CHxCONF : 0x000103C8
MCSPI_CHxSTAT : 0x00000000
MCSPI_CHxCTRL : 0x00000001
MCSPI_TXx : 0x00000000
MCSPI_RXx : 0x00000000
MCSPI_XFERLEVEL : 0x00000000

 

However, there is no action on the SPI clk or mosi pins.

 

Can anyone help me figure out what is wrong? Thanks.
  • 1. You have to do pinmuxing for remaining pins,

         CONTROL_PADCONF_MCSPI1_CLK[31:0]

         CONTROL_PADCONF_MCSPI1_SOMI[31:0]

          CONTROL_PADCONF_MCSPI1_CS1[31:0]

         CONTROL_PADCONF_MCSPI1_CS3[15:0]

    2. Also use MCSPI_CHxCONF[20]FORCE bit to start the transfer if you are using single channel mode.