I want to add that the support value in EZSDK is 796 MHz, not 796.5 MHz.

#define CONFIG_TI8168_DDR3_796 /* Values supported 400,531,675,796 */

Best Regards,

Pavel

Pavel,

I am told from my software colleague about this matter.

And he points me to evm816x.gel, inside it states options of DDR3 - 400, 531, 621, 634, 648, 675, 702, 729, 756, 783, 796 (796.5).

In that file, it defines "DDR3 EMIF Paramters set for 796.5 MHz Clock Frequency" (copy from the comment).

However, from his description about uboot and SDK, it matches your reply and he can boot at 675MHz, but not 796MHz.

To be precise, it would be good if you can clarify whether it is 796MHz or 796.5MHz.

Anyway, this is pretty minor so I collectively take it as 796MHz.

My major concern is that our PCB fails to run at 796MHz, but only at lower frequency settings.

We would like to seek advice & solution to support this 796MHz.

Regards,

Alex

Biser,

Let me check with my colleague about this.

I believe we have not fine tune the DDR3 interface. From the overview, it looks this is the missing process.

We need to accurately fine tune, after we test the DDR interface is functionally working.

Now, I am filling the RatioSeed.xls.

DDR3 clock frequency = 796.5 and CK and DQS trace lengths in inches.

What should I fill for the "Invert Clkout" cell?

Please advise.

Regards,

Alex

Hi Alex,

Actually it is 796.5 MHz. I checked this on my own DM816X EVM.

As I am able to boot with DDR3 on 796.5 MHz, and from what I understand you can not even boot on that frequency (is that correct?), most probably it is a hardware design (PCB) issue.

BR,

Pavel

Hi Pavel,

We have not perform the DDR3 initialization procedures, and we are reading the wiki pages on that.

We measure the CK and DQS traces and input to RatioSeed.xls for both DDR0 and DDR1 EMIF.

In word-wise SW leveling, we run the CCS based program DDR3_slave_ratio_search.out.

The modify the U-boot, and modify the value in file arch/arm/include/asm/arch-ti81xx/ddr_defs_ti816x.h

#if defined(CONFIG_TI816X_DDR3_SW_LEVELING)
/* These values are obtained from the CCS app */
#define RD_DQS_GATE    ((emif == 0) ? 0x1B3 : 0x1B3)
#define RD_DQS        ((emif == 0) ? 0x35 : 0x35)
#define WR_DQS        ((emif == 0) ? 0x93 : 0x93)

#endif

=============================================================================================

From that page, it is advised to perform byte-wise SW leveling at higher frequencies.

We get 4 columns of slave ratio values for each byte lane.

However, where to change in U-boot?

In the same header file "ddr_defs_ti816x.h", we lines like below.

#define WR_DQS_RATIO_0        0x20
#define WR_DQS_RATIO_1        0x20
#define WR_DQS_RATIO_2        0x20
#define WR_DQS_RATIO_3        0x20
But they are for the all the frequency

Or

#if defined(CONFIG_TI816X_DDR3_SW_LEVELING)
#define WR_DQS_RATIO_BYTE_LANE3    ((WR_DQS << 10) | WR_DQS)
#define WR_DQS_RATIO_BYTE_LANE2    ((WR_DQS << 10) | WR_DQS)
#define WR_DQS_RATIO_BYTE_LANE1    ((WR_DQS << 10) | WR_DQS)
#define WR_DQS_RATIO_BYTE_LANE0    ((WR_DQS << 10) | WR_DQS)

#define WR_DATA_RATIO_BYTE_LANE3    (((WR_DQS + 0x40) << 10) | (WR_DQS + 0x40))
#define WR_DATA_RATIO_BYTE_LANE2    (((WR_DQS + 0x40) << 10) | (WR_DQS + 0x40))
#define WR_DATA_RATIO_BYTE_LANE1    (((WR_DQS + 0x40) << 10) | (WR_DQS + 0x40))
#define WR_DATA_RATIO_BYTE_LANE0    (((WR_DQS + 0x40) << 10) | (WR_DQS + 0x40))

#define RD_DQS_RATIO            ((RD_DQS << 10) | RD_DQS)

#define DQS_GATE_BYTE_LANE0        ((RD_DQS_GATE << 10) | RD_DQS_GATE)
#define DQS_GATE_BYTE_LANE1        ((RD_DQS_GATE << 10) | RD_DQS_GATE)
#define DQS_GATE_BYTE_LANE2        ((RD_DQS_GATE << 10) | RD_DQS_GATE)
#define DQS_GATE_BYTE_LANE3        ((RD_DQS_GATE << 10) | RD_DQS_GATE)

#endif    /* CONFIG_TI816X_DDR3_SW_LEVELING */

They are also for the all the frequency.

So can you advise where to make change for byte-wise SW leveling?

Thank you very much for answering.

Regards,

Alex

Open the file arch/arm/include/asm/arch-ti81xx/ddr_defs_ti816x.h
Modify  the value

#if defined(CONFIG_TI816X_DDR3_SW_LEVELING)
/* These values are obtained from the CCS app */
#define RD_DQS_GATE    ((emif == 0) ? 0x1B3 : 0x1B3)
#define RD_DQS        ((emif == 0) ? 0x35 : 0x35)
#define WR_DQS        ((emif == 0) ? 0x93 : 0x93)

#endif

Hi Alex,

What did you get from the RatioSeed Excel spreadsheet? Is the Invert Clkout question still open?

Reading section Obtaining the seed values, it seems to me that you have to get from the RatioSeed (based on the input data) the following output data: WR_DQS, RD_DQS and RD_DQS_GATE

 BR,

Pavel

Also have a look on this patch:

http://arago-project.org/git/projects/?p=u-boot-omap3.git;a=commit;h=bcb0882b791b7c3c60be40bde0416069cb2eb1c2

BR,

Pavel

Hi Pavel,

My colleagues was not able to boot DDR3 at 796.5MHz.

Yes, the Invert Clkout question is still open, we put "0" in the RatioSeed Excel spreadsheet, but we have not find out what it means.

From the excel spreadsheet, we get Seed Values to input to program (WR_DQS, RD_DQS and RD_DQS_GATE

However, my colleague says the CCS based slave ratio search program does not converge to any value, thus does not get any value from command prompt.

Attach the RatioSeed excel for DDR0 EMIF.

Also, do you have any advice and range of value in trace length? Afraid that our trace length is a bit long in byte 0.

We can optimize the trace length and PCB design based on your advice.

Thank you very much.

Regards,

Alex