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Building U-Boot for NOR

Dennis McLeod
Intellectual 925 points

In the PSP U-Boot document, there is a flow chart in the section "NOR Boot".  Is this code and logic already in U-Boot or is it modifications that I would need to make? The Flow-chart illustrates that u-boot determines if it's running from NOR or from DDR, and copies the nor-init code to ddr, executes it, and returns to NOR. What modifications would I need to make in order to initialize address lines A[27:13]..  The doc says "Since ROM code does not initialize all 25 address lines...".   I need to initialize all *27* address lines. Our design uses a 128MB NOR flash, not 64MB. So I need to be able to address the entire address range.

Thank you in advance for any help!

  • 0
    TI__Guru**** 170625 points

    Hi Dennis,

    Please check these threads:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/119275.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/123888.aspx

    More info for NOR boot you can find in:

    http://processors.wiki.ti.com/index.php/DM814x_AM387x_PSP_Flashing_Tools_Guide

    http://processors.wiki.ti.com/index.php/TI81XX_PSP_NOR_Driver_Guide

    http://processors.wiki.ti.com/index.php/TI81XX_PSP_User_Guide#Boot_from_NOR

    Best Regards,

    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 925 points

    Hello Pavel,

    Thank you.. those are most helpful! Can you clarify what Mansoor meant in the discussion at http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/123888.aspx when he said "Just to add on top of that, the NOR boot section in the u-boot user guide is specific to TI EVM and Daughter card." ?  This is what I'm most interesting in learning. That document doesn't really illustrate what changes might need to be made when moving to another design. Our design has GPMC A[26:0] going to a spansion 1G (128MB) NOR flash.

    Its useful information in http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/119275.aspx when the original poster listed lines like "A12 - H2 0xb24 mode 1" but I'm curious where he made that change, how he *learned* where to make that change, etc.

    Thank you again!

    Dennis

  • 0 in reply to Dennis McLeod
    TI__Guru**** 170625 points

    Hello Dennis,

    I think that Mansoor mean that NOR boot section in u-boot user guide is specific for the TI DM814x EVM (from Mistral) which consists of 3 parts: base board, expansion I/O board and LCD panel. NAND and SPI flash are located in the base board, but NOR flash is located in the expansion I/O board (referred as Daughter card in above).

    "A12 - H2 0xb24 mode 1" is :

      A12 - address line (GPMC_A12), H2 is physical device pin, 0xb24 is the offset from the base address, mode 1 is the MultiMuxed mode. But this is valid for C6A8168 device and you are on DM814X device. In your case is "A12 - AF18 0xab8 mode 1"

    I recommend you to read the DM814x TRM, section 4.7.2 XIP memory and section 11 GPMC. Also DM814X data sheet, where all these pins, MuxModes and configuration registers are explained. 

    BR,

    Pavel