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am335x iep interrupt

stfn mdl

hi,

i tried to connect an iep event to an arm isr function (using sys/bios),
but no events are generated in the secr, not even in the srsr register of the pruss.
the timer itself is up and running, generating the 'events' in the pruss iep registers: 
iep_cmp_status and iep_global_status.

following pruss registers were configured in order to get the iep timer running:
global_cfg, compen (not used), cmp_cfg, cmp0 and in the cfg cgr register the enable
bit was set.

is there anything else to do in order to connect an arm isr with an iep event?

ed:   what are the corresponding interrupt numbers for the cmp0-7 events? 
ed2: what i should have mentioned: i assumed polarity_high and and evt_type_edge.
(also tried a few other combination but none of them seems to work neither)

 stefan

 

  • 0
    TI__Mastermind 47731 points

    Hi,

    IEP events or sys events supported by PRU-ICSS is documented in section7- table161 can be mapped to ARM ISR  https://github.com/beagleboard/am335x_pru_package/blob/master/am335xPruReferenceGuide.pdf

    I see that IEP CMP/CAP status is mapped as int Number 7 in the table. IEP global status is not mapped as h/w system event.

    You can map this to ARM ISRs namely PRU_ICSS_EVTOUT0(20) to PRU_ICSS_EVTOUT7 (27) by programming CMR (sys event to channel mapping) and HMR (channel to host mapping) registers. See http://www.ti.com/tool/sysbiossdk-ind-sitara - there is an API prussdrv_pruintc_init to do this mapping easily from A8 application using mapping defined in array here - sdk\protocols\ethercat_slave\include\tiesc_pruss_intc_mapping.h

    However if you need a global IEP status like IEP counter overflow to be exported to A8- you need to assert a software interrupt from PRU to ARM using PRUSS int Num 16 to 31 after polling for the status from PRU..

  • 0 in reply to PratheeshGangadhar

    for the record:
    first of all when using the iep isr, the interrupt has to be configured to polarity_high, type_pulse.
    directly after the mapping to an arm isr the corresponding bit in the cmp_status register and the 
    IEP_TIM_CAP_CMP_EVENT (int num. 7) bit in secr0 has to be cleared to avoid an instant isr 
    call. furthermore this procedure has to be repeated after each isr call. 

    stefan