Progressive to Interlaced

Hi Ran,

Do you mean after capture? It is not possible in capture. Why can't you drop every alternate progressive frame and generate two fields out of other progressive frames?

Thx,

Brijesh

Hi Brijesh,

It does not have to be after capture or during. I am interested if there is a simple way, which is supported in HDVPSS, to do such conversion so that we can encode video which was originated progressive as encoded interlaced video, without expensive manipulations on frames in DDR.

Thanks,

Ran

Hi Brijesh,

Thank you very much for the answer,

Can you please take a look at previous questions too ?

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/209656.aspx

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/209674.aspx

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/209353.aspx

Hi Brijesh,

In vps/vps_cfgDei.h it is documneted in Vps_DeiConfig & Vps_DeiHqConfig structures that there are 4 possible options when using dei and scalar bypass modes:

1 interlaced input , interlaced output
2  interlaced input , progressive output
3 progressive input , interlaced output
4 progressive input , progressive output 

Does Netra support these in DEI & DEIH ? Is the Link/MCFW support such configurations too ? 

Thanks,

Ran

Hi ran,

there is one correction, it cannot do progressive input -> inerlaced output.

Both Netra DEI does support these combinations, McFw supports below combinations

interlaced input , progressive output

progressive input , progressive output 

Thanks,

Brijesh Jadav

Hi Brijesh,

I understand from the answer that also the following combination is NOT supported, right ?

interlaced input , interlaced output

Is it a hardware Limitation ? accodring to sprugx8 there are 3 modes: dei-interlacer, progressive bypass and interlaced bypass.

Thank you very much for your time,

Ran

Hi Ran

yes, this combination is not supported in RDK, but is there any reason why you can't treat interlaced input/output as progressive input/output?

Thx,

Brijesh

Hi Brijesh,

Is this limitation a software RDK Limit (Links limitation), and the driver still support interalced input -> interlaced output ?

I don't mind doing this bypass as if it is input progressive and output progressive as long as the chain will handle the interlaced information all along the chain as needed. Eventually the idea is that the interlaced video will be encoded (as interlaced). Will the encoder encode the video as interlaced or do I need to make some changes for it to work ?

Thanks,

Ran