Bare-metal (no OS) Example

At this time there is no non-OS reference code.

Next are comments about this post that are not requested and I must clarify that I learn this initially for OMAP3 and some of the information is OMAP4 related.

There are documents like TRM and DM that explains the boot up process and what needs to be initialized in order to get both processors sides running, for what I read there is a sequence that is followed to get them up and running.

About the "with-OS", then you will need to know about the booting HW too, this is about the boot sequence and booting selection pins and how it is handled, it means replacing xloader, uboot and kernel stuffs too.

For what I think of this is that compilers are going to work the same way to generate the code, I haven't go to assembler code yet since using C language offers some facilities to get portable code, but there are some instructions sets pdf's too that describes assembler language.

When you refers to DSP (M3-Ducati) does it is meant to run on top of Bios tools? you are talking about A9 I support it is OMAP4, Sys/Bios tools have the OS and related code like threads message box and others to get it directly working, if you get it initialized from A9 and you fulfill what is needed you must be able to load a binary like the ones that loads BIOS tools, at least is what I know. Other tools like framework-components, codec-engine, xdais like xdc tools osal and IPC are that tools or standards that helps to program in either side, some are specific to one processor or other. One entry point is http://omapedia.org/wiki/RPMsg_BIOS_Sources#SYS.2FBIOS_Tools or the next link http://e2e.ti.com/support/omap/f/849/p/191653/686470.aspx#686470 about CCS and stuffs that can be made using it. RPMsg code is the one that load/communicate to Ducati side it could be a starting point to stablish communication between processors, one link http://omapedia.org/wiki/Category:RPMsg.

Probably using the SYS/BIOS functions is not ok if you are not going to use it like a OS, this it's definition:

http://processors.wiki.ti.com/index.php/Category:SYSBIOS
"SYS/BIOS - SYS/BIOS is an advanced real-time operating system from Texas Instruments for use in a wide range of DSPs, ARMs, and microcontrollers."

But for what I read time back you could require to have some code or OS to process the instructions at the DSP side depending on your configuration and a IPC communication between processors.

Some of these documents are in the public part but some of them must be under NDA, if you cannot find one in public area you may need to contact your TI Representative and ask what documents are available.

Ad 2. If you don't really want to use DSP functionallity, I think that advice to look for SYS/BIOS examples is wrong.

Ad 1. & 3. I never used CCS5, I think it's for small TI DSPs. Is it targeted to OMAPs anyway?

I would:

Stick to ARM-GCC with Eclipse (if you haven't got access to powerful tools like RealView Toolchain) and, of course, OpenOCD for flashing/debugging.

Give up on second core, unless you are going to implement any SMP thread-scheduling mechanism there, just don't even boot core1 and only operate on core0. 1GHZ is edge cutting speed for bare metal app IMO.

Consider some basic DVFS to reduce heating (pretty hard to do efficiently without thread scheduling, so use some simple things like tuning clock down to 300MHz while delaying something)

Treat it like any other ARM, in theory even example for some LPC23xx should do after you modify it a bit.

Replacing linux kernel with the wanted bare metal binary and still use original X-Loader and Uboot, so it does all necessary initialisation. So set up your linker script to have same entrypoint as linux kernel and use mkbootimg from Android toolkit to get boot.img.

Regards

Dominik

Thanks for the responses.  Let me pose the question a little bit differently.

I'm still trying to get familiar with the environment and what is available.  I have been reading the user guide for the OMAP4460 and also found the following link...

http://omappedia.org/wiki/Bootloader_Project

I understand that the initial processor that executes code out of reset is the Cortex-A9 Core 0.  This processor executes code from ROM which looks for a valid image to load into (internal) SRAM to be executed.  In the diagram in the link, this is the "X-Loader" code.

Here is what would be very useful for my project:

1. The "X-Loader" source code.  Is this available?

2. The ability to re-build the "X-Loader" source code for the Cortex-A9.  Can this be done with CCS tools? 

3. The ability to halt the Cortex-A9 processor and debug my custom code (based on the original "X-Loader" code). 

It looks like from the documentation that the OMAP always boots from ROM and copies an image to SRAM - is this correct or is there a way to bootstrap the chip so that it boots directly from internal SRAM?  The thinking is that if the chip boots from SRAM directly then using a debugger to load SRAM directly would be more straightforward...

Thanks very much,

Errett

OMAP4 TRM can be downloaded from

http://www.ti.com/general/docs/wtbu/wtbudocumentcenter.tsp?templateId=6123&navigationId=12037

search the page for 4430, 4460 or 4470 respectively.

+ in case you didn't know about this site (I assume you didn't because you asked for x-loader sources)

http://omapzoom.org/

Dominik,

Are there opened questions on this thread? If not, could you please verify an answer?

Thank you,

Magdalena