• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 98 subscribers
  • Views 507 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

c6678 multiple master access to msm ram question

si cheng
Expert 2685 points
Other Parts Discussed in Thread: TMS320C6678

hello:

MSM RAM has two buffers, one is Ping Buffer, anoter is Pong Buffer, first I get  half data from my ddr, and get another half data from another DSP from SRIO, these data is stored in Ping Buffer , the notify 8 corepac to handle their  data , and  at the same time , I get data from my ddr and data from SRIO to Pong Buffer backgound,

I hope that when the corepacs are processing the current data  and the next data is transfered backgound. 

Now I have a wonder , as the msm ram has 4 banks ,and is interlacing,

 when EDMA transfer data from ddr to msm ram,srio is transferring data to msm ram at the same time , this moment ,the EDMA  will access the 4banks at one access, 

SRIO will wait EDMA to access MSM RAM over, and corepacs will wait too. and this will lead to the access efficiency poor!

So I am not sure what should I do to achieve the high efficiency  when corepac ,EDMA, and SRIO to aceess MSM RAM at the same time! 

thanks!

  • 0
    TI__Mastermind 30825 points

    I'd suggest reading the Throughput Performance Guide which can be found in the Application Notes section of the TMS320C6678 <-- product page. 

    The MSMC should be able to accommodate the ping pong access from SRIO and DDR (over EDMA) at the same time w/ minimal overhead.  It would interleave the accesses and the MSMC RAM has a very large bandwidth.

    If you're experiencing trouble with the performance let us know.

    Best Regards,
    Chad

  • 0 in reply to Chad Courtney
    Expert 2685 points

    hello Chad:

    my project has following cases:

    1.  8 cores get theri  respective  data from Ping Buffer in MSMC RAM simultaneously, at the same time, the EDMA0 transfer data from ddr to Pong Buffer and received data from  hyperlink or SRIO to Ping Buffer

    2   8 cores get theri  respective  data from Ping Buffer simultaneously, at the same time, EDMA0 transfers Pong Buffer data from MSMC RAM to DDR  OR  to hyperlink AND SRIO transfer Pong from MSMC RAM to remote DSP MSMC RAM


    Because at the same time , 8 corepacs read Ping Buffer and EDMA , SRIO read or write Pong Buffer, I wonder these masters maybe Conflict when they access MSMC RAM at the same time, and these masters' access bandwith maybe decrease than only one master accessing the MSMC RAM! 

    Thanks!

  • 0 in reply to si cheng
    TI__Mastermind 30825 points

    Again, I'll suggest that you read the Throughput Application note so you understand a bit more about the MSMC bandwidth.  It is capably have handling multiple data threads coming at it simultaneously.

    Do you have more data on what type of actually throughput you need? 

    Also, if you have 8 cores processing this, it may be better to push data to their local L2 memories individually.  Note that the cross core coherency of MSMC RAM must be maintained by the individual cores (i.e. if Core0 is has cached MSMC RAM space of PONG buffer in L2 and modified this value it remains in L2 until a writeback or eviction is performed by Core0.  If Core1 accesses the same MSMC RAM space of PONG after this modification but before the writeback/eviction has occured it will have stale data.)  This is more likely to be your major concern if all cores are processing the same data in MSMC.

    If this isn't a concern because they're all processing separate pieces, then you could be going directly to the cores L2s.

    Best Regards,

    Chad