dmtimerCounter.c not getting to the ISR

John Conover

Hi,

We are currently working on the BeagleBone and have interfaced it to an FPGA. Because we needed to do pin muxing we did not do

use the beaglebone gel files or target in the general setup(we use the AM335X). I've tried to install a timer ISR by using the example

in dmtimerCounter.c. I am currently running the exact calls in the demo:

The timer 2 registers look good and the timer is counting up:

0x4804002C  00000002

0x48040030  00000002

0x48040034  00000000

0x48040038  00000003 Auto reload

0x4804003C  FF9ADD38 Timer is counting

0x48040040  FF000000 Reload value

So it seems that when the timer expires the ISR is not getting triggered. Is there something in the beaglebone gel or

configuration that allows the ISR to happen that is not in the AM335X configuration. We did note that in the DMTimerAintcConfigure/IntSystemEnable()

call the comment "This API enables the system interrupt in AINTC. However, for the interrupt generation, make sure that the interrupt is
enabled at the peripheral level also. " Could this be what were missing?

Thanks

over 13 years ago

0 Sujith KV over 13 years ago

TI__Intellectual 2525 points

Hi John,

Have you enabled IRQ in ARM using MasterIRQEnable() API ? This needs to be done in application. Our startup code doesnt enable IRQ.

Regards,

Sujith.

0 John Conover over 13 years ago in reply to Sujith KV

Genius 4350 points

Hi Sujith,

Yes we did enable the IRQ just a little further down from the original DMTimer code as we also were

setting up the fpga DMA. The only thing we don't do that the original file does is set up the UART.

/* This function will enable clocks for the DMTimer2 instance */
    DMTimer2ModuleClkConfig();
    DMTimerAintcConfigure();    /* Register DMTimer2 interrupts on to AINTC */
    DMTimerSetUp();     /* Perform the necessary configurations for DMTimer */
    DMTimerIntEnable(SOC_DMTIMER_2_REGS, DMTIMER_INT_OVF_EN_FLAG);     /* Enable the DMTimer interrupts */
    DMTimerEnable(SOC_DMTIMER_2_REGS);      /* Start the DMTimer */

    /* Initialize EDMA3 Controller */
    /* Initialization of EDMA3 */
    EDMA3Init(SOC_EDMA30CC_0_REGS, EVT_QUEUE_NUM);

    /* Register EDMA3 Interrupts */
    ConfigureAINTCIntEDMA3();

    /* Enabling IRQ in CPSR of ARM processor. */
    IntMasterIRQEnable();                                                       <-- Enabled it here

Thanks,

John C.

0 John Conover over 13 years ago in reply to John Conover

Genius 4350 points

A final update to this issue. It seems that after the setup calls for DTimer we had a call to ConfigureAINTCIntEDMA3(), which then wiped out the ISR

setup for the DTimer. We moved the DTimer ISR setup into ConfigureAINTCIntEDMA3 and then commented out DMTimerAintcConfigure() and

every works as advertised.

Thanks.

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dmtimerCounter.c not getting to the ISR