I am trying to Enable the test modes in USB2.0 port inside the USB3.0(XHCI) page:300 in "xHCI_Specification_for_USB.pdf" and page:7069 in "OMAP543x_ES1.0_NDA_TRM_vC.pdf". We followed the test mode sequence mentioned in the 4.19.6 section of xHCI spec. But always we are reading '0" from Port Test Control bits of PORTPMSC2 register even after setting the specific test mode value in PORTPMSC2 register like 0x1 for Test J_STATE.
Here I pasted the code snippet, please let me know if I missed any configuration to enable the test patterns.
#define USBOTGSS_CAPLENGTH 0x4A030000
#define USBOTGSS_HCSPARAMS1 0x0004
#define USBOTGSS_HCCPARAMS 0x0010
#define USBOTGSS_USBCMD 0x0020
#define USBOTGSS_USBSTS 0x0024
#define USBOTGSS_CONFIG 0x0058
#define USBOTGSS_PORTSC1 0x0420
#define USBOTGSS_PORTSC2 0x0430
#define USBOTGSS_PORTPMSC2 0x0434
#define USBOTGSS_GCTL 0xC110
#define USBOTGSS_GSTS 0xC118
#define USBOTGSS_DCFG 0xC700
#define USBOTGSS_DCTL 0xC704
#define USBOTGSS_DSTS 0xC70C
#define USBOTGSS_OCTL 0xCC04
#define USBOTGSS_OSTS 0xCC10
#define PORTSC2_POWER (1 << 9)
#define RUN_STOP_BIT (1 << 0)
#define HCH_BIT (1 << 0)
#define DEVSPD_BIT (7 << 0)
#define PERIMODE_BIT (1 << 6)
#define HCRST_BIT (1 << 1)
#define PRTCAPDIR_BITS (1 << 12)
#define Reg32_Write( BaseAddress, OffsetAddress, Value ) \
*((volatile _uint32 *)( (_uint8 *)BaseAddress + OffsetAddress ) ) = Value
#define Reg32_Read( BaseAddress, OffsetAddress ) \
*((volatile _uint32 *)((_uint8 *)BaseAddress + OffsetAddress ) )
/*
base_address = after mmap of the USB OTG Physical address: 0x4A030000
test_mode = USB port test pattern like 1 = Test J_STATE, 2 = Test K_STATE etc.
*/
void test_mode_sequence(unsigned int *base_address, int test_mode)
{
unsigned int pstatus = 0, usb_cmd = 0, portpmsc = 0, stat = 0;
unsigned char test = 0;
int i = 100;
stat = Reg32_Read( base_address, USBOTGSS_USBSTS );
printf("Stat = %x\n",stat);
/* Disable all Device slots - set MAXSLOTSEN bits in USBOTGSS_CONFIG register to 0 */
Reg8_Write(base_address, USBOTGSS_CONFIG, 0x0);
/* All ports be in the disabled state (PP = 0) */
pstatus = Reg32_Read(base_address, USBOTGSS_PORTSC1);
printf("PORTSC1-1 = %x\n",pstatus); //output: pstatus = 0x2A0
Reg32_Write( base_address, USBOTGSS_PORTSC1 , pstatus &= ~PORTSC2_POWER );
pstatus = Reg32_Read(base_address, USBOTGSS_PORTSC1); //output: pstatus = 0x80
pstatus = Reg32_Read(base_address, USBOTGSS_PORTSC2);
printf("PORTSC2 = %x\n",pstatus); //output: pstatus = 0x2A0
Reg32_Write( base_address, USBOTGSS_PORTSC2 , pstatus &= ~PORTSC2_POWER );
pstatus = Reg32_Read(base_address, USBOTGSS_PORTSC2); //output: pstatus = 0x80
delay(100);
pstatus = Reg32_Read(base_address, USBOTGSS_PORTSC2);
printf("pstatus for port 2= %x\n",pstatus);
/* set R/S bit in USBCMD register to 0 and wait for halted state (HCH)
* bit in USBSTS register to be 1 */
usb_cmd = Reg32_Read(base_address, USBOTGSS_USBCMD);
Reg32_Write( base_address, USBOTGSS_USBCMD , (usb_cmd & ~RUN_STOP_BIT) );
printf("usb_cmd = 0x%x\n",usb_cmd);
while ( !( Reg32_Read( base_address, USBOTGSS_USBSTS ) & HCH_BIT ) && --i )
delay( 10 );
printf("i = %d\n",i);
/* set port test control field in PORTPMSC register with corresponding test mode value */
portpmsc = Reg32_Read(base_address, USBOTGSS_PORTPMSC2);
printf("portpmsc = %x\n",portpmsc); //output: pstatus = 0x0
portpmsc &= ~0xF0000000; // clear test mode bits
Reg32_Write( base_address, USBOTGSS_PORTPMSC2, (portpmsc | (test_mode << 28)) ); /**** Ex: test_mode = 0x01 i.e Test J_STATE ****/
delay(100);
pstatus = Reg32_Read(base_address, USBOTGSS_PORTSC2);
printf("pstatus = %x\n",pstatus); //output: pstatus = 0x80
portpmsc = Reg32_Read(base_address, USBOTGSS_PORTPMSC2);
printf("PMSC = %x\n",portpmsc); //output: pstatus = 0x0, here I expect 0x1XXXXXXX
usb_cmd = Reg32_Read(base_address, USBOTGSS_USBCMD);
Reg32_Write( base_address, USBOTGSS_USBCMD , usb_cmd | HCRST_BIT );
while ( ( Reg32_Read( base_address, USBOTGSS_USBCMD ) & HCRST_BIT ) && --i )
delay( 10 );
}
OMAP543x_ES1.0_NDA_TRM_vC.pdf
