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A ECC problem

liang
Intellectual 290 points

   Hello,all!

         Recently ,i have  been testing  DDR3 within a C6678 board designed by our employee,since the DDR work normal with signal word read  or write,

we try to test  DDR  using EDMA3, and the problem is when we  moved data form DDR3 to L2 (read from DDR ) , some data in L2 did not math with the

data in DDR3 .but when we move data from L2 to DDR3,it work ok,the data mathed. can you give us some suggestion about this problem ?

       another problem is about the ECC,we want to use ECC to do error correction , so we enable the ECC as  DDR3 cotroller  user guider suggested.

the problem is the first 128k memory  space in DDR3 is almost 0x00000000 after we enable the ECC, and we can't wirte value to the first 128k memory spce ,

but the remained memory space work normal ,we don't know why this happened? can somebody give us some suggestions ? 

  

  • 0
    TI__Mastermind 46460 points

    Liang,

    You need to help the customer step through this validation in multiple steps.

    1. You imply that the customer's design correctly configures the DDR3 memory and that it is properly functioning.  Have they verified this?  They should run a simple memory test that validates all addressible DDR3 memory that is executed from the CPU with caching disabled.  A simple test is to write the address of each 32-bit addressible word to the memory and to then read it back.  It is important to have successful results from this test before proceeding.  Proper XMC copnfiguration will be needed to test all of the memory.
    2. EDMA transfers must be carefully mamaged.  I recommend that you execute a test program to move blocks via EDMA from L2 to L2 to verify proper configuration and understanding.  Then, once this is complete and after you know that the DDR3 memory is robust, you can expand this to include DDR3 transfers.  You will need to make sure to set up the XMC correctly for this as well.
    3. Enabling ECC requires multiple steps to get the memory properly initialized and protected.  We will address this after the items above are closed.

    Tom

     

  • 0 in reply to Tom Johnson 16214
    Prodigy 20 points

    I use the C6678 on our Design, the ddr3 is a 64 bit interface plus 8 bits of ecc. With Ecc disabled the DDR3 has been setup, and successfully runs through all memory test and we can load code into the DDR3 and run from there. 

    The problem is If I enable ECC, then only 64 bit write and reads work.  32 bit writes corrupt the ECC and reads report the failure.

    Is this normal behavior for the C6678?

    The statement below infers that a write 32 cannot correctly produce a proper 64 bit ECC code.

    Does this mean that 32 bit writes cannot be issued, ever?

    Is there some other note describing an added latency that might be applied, where a read/modify write is issued?

    sprugv8c.pdf 2.16 ECC Note

    A write access with a byte count that is not a multiple of 64 bit quanta,

    or with a non-64-bit-aligned address performed within the address range protected by ecc will result in a write ecc error interrupt.

  • 0 in reply to Richard dusek
    TI__Mastermind 46460 points

    Rick,

    I believe your understanding is correct.  If you wish to operate with ECC enabled, you have to manage the accesses such that only aligned 64-bit writes occur.  The DDR3 controller in the C6678 does not support a read-modify-write functionality to allow non-aligned writes.  This management can be accomplished by making the memory area protected by ECC only accessible from the CPUs through cache accesses.  All cache line writes will be 64-bit aligned writes.  Similarly, you can move blocks from peripherals using EDMA with 64-bit aligned writes.  Note this is only an issue with writes.  All reads from the memory are 64-bit aligned even if the bus master only requests a single byte.

    Tom