We have custom design using DM6467 VPIF connected to an FPGA, FPGA uses to produce BT1120 video. When trigger event occurs, FPGA interrupts capturing video and sends a trigger frame, if interrupted frame is incompleted, I want know how to set VPIF registers to achieves BT1120 specification and faster responding?
In our design, if capturing frame is interrupted, we set eav2sav=128, and sav2eav=24 to complete bt1120 timing. But the first trigger frame will lost occasionally. We don't know why, and how to settle it?
Thanks
Richard You