• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 97 subscribers
  • Views 352 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DM6467 VPIF

Richard You
Intellectual 270 points

We have custom design using DM6467 VPIF connected to an FPGA, FPGA uses to produce BT1120 video. When trigger event occurs, FPGA interrupts capturing video and sends a trigger frame, if interrupted frame is incompleted, I want know how to set VPIF registers to achieves BT1120 specification and faster responding?

In our design, if capturing frame is interrupted, we set eav2sav=128, and sav2eav=24 to complete bt1120 timing. But the first trigger frame will lost occasionally. We don't know why, and how to settle it?

Thanks

Richard You

  • 0
    TI__Guru**** 477995 points

    Hi Richard,

     

    Video port in DM6467 is very simple, you just require to configure horizontal and vertical timing information and it will send the data out accordingly. Please refer to the davincihd_capture.c file in the kernel to get the idea about how to program these registers.

    I did not get how you are using VPIF. can you please explain it in detail?

     

    Thanks,

    Brijesh Jadav

  • 0 in reply to Brijesh Jadav
    Intellectual 270 points

    Hi Jadav,

    In our application, FPGA generates BT1120 video timing, and outputs to VPIF, In normal condition, VPIF can work correctly.  We configure VPIF as follow:

    w=1600, h=1210, eav2sav=128, sav2eav=1934, l1=1, l3=3, l5=1213, vsize=1213.

    But when externel event occurs, FPGA must discard current frame, and output a new one, in this condition, the discarded frame is not completed, But FPGA must asserts VPIF it is a completed frame, FPGA does the following things:

    If frame is interrpted at N line, the rest lines is generated by FPGA, for each line: eav2sav=128, and sav2eav=24, Total line number is 1213 - N lines.

    In most case VPIF can work well, but sometimes VPIF will lost the new frame. If snap 3 frames one time, only 2, 3 frame is received, and the first one is lost.

    VPIF technical document don't refer to this application, We want to know, Our setting is satisfying VPIF timing, if not, How to do?

    Thanks,

    Richard You