Hi,
for the validation of our OMAP L137 based custom board, I have to validate that I2S data are well managed...
Unlike the EVM board, our custom board does not have integrated codec . McAsp signals come from an expansion connector : AXR1[0to5] are connected and also clock reception signals (AHCLKR1, ACLKR1 and AFSR1)
Note: the transmit clock pins are not connected.
To generate I2s input signals, TLV320AIC3254 EVM is used. Thanks to pure path, I have wired analog input straight to digital output (DOUT) and connector P22 (digital output of TLV320AIC3254 EVM) is connected to our expansion connector.
To validate the system, I wanted to perform a loopthrough (transmit the data without modifications right back to the EVM codec) so I consider the McAsp echo application from quickStartOMAPL1x_rCSL-2.0-Setup (developped for OMAP L138, it has been adapted for OMAP L137)
Default settings have also been modified, considering that Rx clock signals were externals and Tx remains internals (my Tx Clock signals are not connected).
My input is AXR1[5] and output AXR1[1], so modify the code as follow:
void McASPInit(void)
{
/* Put McASP in Reset by programming the global control registers */
CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XFRST, RESET);
CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSMRST, RESET);
CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSRCLR, CLEAR);
CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XHCLKRST, RESET);
CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_XCLKRST, RESET);
//Keep all Rx Clocks In Reset
CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RFRST, RESET);
CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSMRST, RESET);
CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSRCLR, CLEAR);
CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RHCLKRST, RESET);
CSL_FINST(mcaspRegs->GBLCTL, MCASP_GBLCTL_RCLKRST, RESET);
//Disable Tx FIFO
CSL_FINST(afifoRegs->WFIFOCTL, AFIFO_WFIFOCTL_WENA, DISABLED);
//Disable Rx FIFO
CSL_FINST(afifoRegs->RFIFOCTL, AFIFO_RFIFOCTL_RENA, DISABLED);
//Configure the receive bit stream for 32 bit I2S.
CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RDATDLY, 1BIT); //Ignore First Bit due to I2S
CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RRVRS, MSBFIRST);
//Pad Unused Bits with value in bit 0
CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RPAD, ZERO);
//32 bit slot size, though only 24 bit word size
CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RSSZ, 32BITS);
//No Rotation needed
CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RROT, NONE);
//Read XRBUF[n] on the Peripheral Configuration Port (For Now -> May change to the DMA Later)
CSL_FINST(mcaspRegs->RFMT, MCASP_RFMT_RBUSEL, VBUS);
//Mask Off Unused Bits -> For Now, well leave all unmasked -> May change later.
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK31, NOMASK); //Audio Data MSB
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK30, NOMASK); //Audio Data MSB-1
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK29, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK28, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK27, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK26, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK25, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK24, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK23, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK22, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK21, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK20, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK19, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK18, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK17, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK16, NOMASK); //Audio Data Bit LSB (16 bit)
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK15, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK14, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK13, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK12, NOMASK); //Audio Data Bit LSB (20 bit)
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK11, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK10, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK9, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK8, NOMASK); //Audio Data LSB (24 bit)
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK7, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK6, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK5, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK4, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK3, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK2, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK1, NOMASK);
CSL_FINST(mcaspRegs->RMASK, MCASP_RMASK_RMASK0, NOMASK);
/* Receive Frame Sync Control Register */
//Configure Frame Sync for 2 Channel TDM
CSL_FINST(mcaspRegs->AFSRCTL, MCASP_AFSRCTL_RMOD, I2S);
//Configure Frame Sync to last length of word
CSL_FINST(mcaspRegs->AFSRCTL, MCASP_AFSRCTL_FRWID, WORD);
//Configure Frame Sync for EXTERNAL generation
CSL_FINST(mcaspRegs->AFSRCTL, MCASP_AFSRCTL_FSRM, EXTERNAL);
//Configure Frame Sync that falling edge starts new channel for I2S
CSL_FINST(mcaspRegs->AFSRCTL, MCASP_AFSRCTL_FSRP, FALLINGEDGE);
/* Receive Bit Clock Control Register */
//Sample bit on Rising Edge of ACLKR
CSL_FINST(mcaspRegs->ACLKRCTL, MCASP_ACLKRCTL_CLKRP, RISINGEDGE);
//Clock Generated by OMAP-L138
CSL_FINST(mcaspRegs->ACLKRCTL, MCASP_ACLKRCTL_CLKRM, EXTERNAL);
CSL_FINS(mcaspRegs->ACLKRCTL, MCASP_ACLKRCTL_CLKRDIV, 0); //Irrelvant when ASYNC = 0
/*Receive High Frequency Clock Control Register (Master Clock)*/
CSL_FINST(mcaspRegs->AHCLKRCTL, MCASP_AHCLKRCTL_HCLKRM, EXTERNAL);
CSL_FINST(mcaspRegs->AHCLKRCTL, MCASP_AHCLKRCTL_HCLKRP, NOTINVERTED);
/*Receive TDM Time Slot Register */
//Slots 31-2 Inactive
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS31, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS30, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS29, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS28, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS27, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS26, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS25, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS24, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS23, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS22, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS21, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS20, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS19, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS18, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS17, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS16, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS15, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS14, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS13, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS12, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS11, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS10, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS9, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS8, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS7, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS6, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS5, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS4, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS3, INACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS2, INACTIVE);
//Slots 0,1 Active for I2S
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS1, ACTIVE);
CSL_FINST(mcaspRegs->RTDM, MCASP_RTDM_RTDMS0, ACTIVE);
/* Receiver Interrupt Control Register */
//Disable Start of Frame Interrupt
CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RSTAFRM, DISABLE);
//Disable Data Read Interrupt
CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RDATA, DISABLE);
//Disable Recive Last Time Slot Interrupt
CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RLAST, DISABLE);
//Disable DMA Error Interrupt
CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RDMAERR, DISABLE);
//Disable Clock Failure Error Interrupt
CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RCKFAIL, DISABLE);
//Disable Unexpected FrameSync Error Interrupt
CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_RSYNCERR, DISABLE);
//Disable Reciever Overrun Error Interrupt
CSL_FINST(mcaspRegs->RINTCTL, MCASP_RINTCTL_ROVRN, DISABLE);
/* Recieve Serializer */
//Keep All Bits unmaksed
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK31, NOMASK); //Audio Data Bit MSB
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK30, NOMASK); //Audio Data Bit MSB-1
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK29, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK28, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK27, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK26, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK25, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK24, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK23, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK22, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK21, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK20, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK19, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK18, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK17, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK16, NOMASK); //Audio Data Bit LSB (16 bit)
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK15, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK14, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK13, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK12, NOMASK); //Audio Data Bit LSB (20 bit)
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK11, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK10, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK9, NOMASK); //Audio Data Bit LSB +1
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK8, NOMASK); //Audio Data Bit LSB (24 bit)
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK7, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK6, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK5, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK4, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK3, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK2, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK1, NOMASK);
CSL_FINST(mcaspRegs->XMASK, MCASP_XMASK_XMASK0, NOMASK);
CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XDATDLY, 0BIT); /
CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XRVRS, MSBFIRST);
CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XPAD, ZERO);
CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XSSZ, 32BITS);
CSL_FINS(mcaspRegs->XFMT, MCASP_XFMT_XPBIT, 0);
CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XROT, NONE);
CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XBUSEL, VBUS);
/*Transmit Frame Sync Control Register */
//Frame Sync is configured for I2S
CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_XMOD, I2S);
//Frame Sync Length is Word
CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_FXWID, WORD);
//Frame Sync is EXTERNALly generated by XCLK
CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_FSXM, INTERNAL);
//Falled Edige indicates beginning of new word
CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_FSXP, FALLINGEDGE);
/* ACLKX = 3.072MHz = 64Fs = 256Fs/4 */
CSL_FINST(mcaspRegs->ACLKXCTL, MCASP_ACLKXCTL_CLKXP, RISINGEDGE);
CSL_FINST(mcaspRegs->ACLKXCTL, MCASP_ACLKXCTL_ASYNC, ASYNC); //ACLKR / nACLKX
CSL_FINST(mcaspRegs->ACLKXCTL, MCASP_ACLKXCTL_CLKXM, INTERNAL);
CSL_FINS(mcaspRegs->ACLKXCTL, MCASP_ACLKXCTL_CLKXDIV, 7);
/* Transmit High Frequency Clock Register*/
// Generate High Frequency Clock Source Externally from 24.576MHz XTAL
CSL_FINST(mcaspRegs->AHCLKXCTL, MCASP_AHCLKXCTL_HCLKXM, INTERNAL);
CSL_FINST(mcaspRegs->AHCLKXCTL, MCASP_AHCLKXCTL_HCLKXP, NOTINVERTED);
// AHCLKX = 24.576MHz
CSL_FINS(mcaspRegs->AHCLKXCTL, MCASP_AHCLKXCTL_HCLKXDIV, 0);
/* Transmit TDM Time Slot Register */
//32-2 should be inactive
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS31, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS30, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS29, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS28, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS27, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS26, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS25, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS24, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS23, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS22, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS21, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS20, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS19, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS18, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS17, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS16, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS15, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS14, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS13, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS12, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS11, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS10, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS9, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS8, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS7, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS6, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS5, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS4, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS3, INACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS2, INACTIVE);
//Active Slots 0/1 for I2S
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS1, ACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS0, ACTIVE);
/*Transmit Interrupt Control Register */
//Disable All Transmit McASP Interrupts
CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XSTAFRM, DISABLE);
CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XDATA, ENABLE);
CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XLAST, DISABLE);
CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XDMAERR, DISABLE);
CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XCKFAIL, DISABLE);
CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XSYNCERR, DISABLE);
CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XUNDRN, DISABLE);
CSL_FINST(mcaspRegs->XCLKCHK, MCASP_XCLKCHK_XPS, DIVBY4);
CSL_FINS(mcaspRegs->XCLKCHK, MCASP_XCLKCHK_XMIN, 0x2F);
CSL_FINS(mcaspRegs->XCLKCHK, MCASP_XCLKCHK_XMAX, 0x32);
//Configure Serializer 1 to be a Transmit Serializer
CSL_FINST(mcaspRegs->SRCTL1, MCASP_SRCTL1_SRMOD, XMT);
//Configure Serializer 4 to be a Recieve Serializer
CSL_FINST(mcaspRegs->SRCTL5, MCASP_SRCTL5_SRMOD, RCV);
//Configure AHCLKX, ACLKX, AFSX, AXR11, AXR12 as McASP Pins vs. GPIO Pins
CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AFSX, MCASP);
CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AHCLKX, MCASP);
CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_ACLKX, MCASP);
CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AXR5, MCASP);
CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AXR1, MCASP);
/* PDIR Register */
//Configure the AHCLKX, ACLKX, AFSX, AXR11 as Output Pins to send Clocks/Data from TLV320AIC3106
CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AFSX, OUTPUT);
CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AHCLKX, INPUT);
CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_ACLKX, OUTPUT);
CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AXR1, OUTPUT);
//Configure AXR11 as Input to Get Data from TLV320AIC3106
CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AFSR, INPUT);
CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AHCLKR, INPUT);
CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_ACLKR, INPUT);
CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AXR5, INPUT);
//Disable DIT Portion of McASP
CSL_FINST(mcaspRegs->DITCTL, MCASP_DITCTL_DITEN, DISABLE);
//Configure Digital Loopback
CSL_FINST(mcaspRegs->DLBCTL, MCASP_DLBCTL_DLBEN, DISABLE);
CSL_FINST(mcaspRegs->DLBCTL, MCASP_DLBCTL_ORD, XMTODD);
//Configure AMUTE Pin to drive when any Error Occurs
CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_XDMAERR, DISABLE);
CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_RDMAERR, DISABLE);
CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_XCKFAIL, DISABLE);
CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_RCKFAIL, DISABLE);
CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_XUNDRN, DISABLE);
CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_ROVRN, DISABLE);
CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_XUNDRN, DISABLE);
CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_ROVRN, DISABLE);
//Disable AMUTEIN Pin to isolate from LogicPD HW status
CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_INSTAT, INACTIVE);
//Disable Drive on AMUTEOUT when AMUTEIN error is active
CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_INEN, DISABLE);
//Configure AMUTE Input Logic Level to High
CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_INPOL, ACTHIGH);
//Disable AMUTE PIN
CSL_FINST(mcaspRegs->AMUTE, MCASP_AMUTE_MUTEN, DISABLE);
return;
}
void McASPStart(void){
if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XHCLKRST)!=CSL_MCASP_GBLCTL_XHCLKRST_ACTIVE){
//Start Transmit High Frequency clock if not active
CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XHCLKRST, ACTIVE);
//Stall until GBLCTL reads back to ensure it was latched by the logic
while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XHCLKRST)!=CSL_MCASP_GBLCTL_XHCLKRST_ACTIVE);
}
if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RHCLKRST)!=CSL_MCASP_GBLCTL_RHCLKRST_ACTIVE){
//Start Recieve High Frequency clock
CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RHCLKRST, ACTIVE);
//Stall until GBLCTL reads back to ensure it was latched by the logic
while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RHCLKRST)!=CSL_MCASP_GBLCTL_RHCLKRST_ACTIVE);
}
if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XCLKRST)!=CSL_MCASP_GBLCTL_XCLKRST_ACTIVE){
//Start Transmit High Frequency clock if not active
CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XCLKRST, ACTIVE);
//Stall until GBLCTL reads back to ensure it was latched by the logic
while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XCLKRST)!=CSL_MCASP_GBLCTL_XCLKRST_ACTIVE);
}
if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RCLKRST)!=CSL_MCASP_GBLCTL_RCLKRST_ACTIVE){
//Start Recieve Serial Clock
CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RCLKRST, ACTIVE);
//Stall until GBLCTL reads back to ensure it was latched by the logic
while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RCLKRST)!=CSL_MCASP_GBLCTL_RCLKRST_ACTIVE);
}
//For now we use CPU polling -> so no action is required
mcaspRegs->XSTAT = 0x0000FFFF;
mcaspRegs->RSTAT = 0x0000FFFF;
if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSRCLR)!=CSL_MCASP_GBLCTL_XSRCLR_ACTIVE){
//Start Recieve Serial Clock
CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XSRCLR, ACTIVE);
// Stall until GBLCTL reads back to ensure it was latched by the logic
while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSRCLR)!=CSL_MCASP_GBLCTL_XSRCLR_ACTIVE);
}
if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSRCLR)!=CSL_MCASP_GBLCTL_RSRCLR_ACTIVE){
//Start Recieve Serial Clock
CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RSRCLR, ACTIVE);
// Stall until GBLCTL reads back to ensure it was latched by the logic
while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSRCLR)!=CSL_MCASP_GBLCTL_RSRCLR_ACTIVE);
}
if(CSL_FEXT(mcaspRegs->XSTAT, MCASP_XSTAT_XDATA)==CSL_MCASP_XSTAT_XDATA_YES){
mcaspRegs->XBUF1 = 0xFFFFFFFFu;
}
/*[9] Release the State Machines from Reset */
if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSMRST)!=CSL_MCASP_GBLCTL_XSMRST_ACTIVE){
//Start Recieve Serial Clock
CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XSMRST, ACTIVE);
// Stall until GBLCTL reads back to ensure it was latched by the logic
while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XSMRST)!=CSL_MCASP_GBLCTL_XSMRST_ACTIVE);
}
if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSMRST)!=CSL_MCASP_GBLCTL_RSMRST_ACTIVE){
//Start Recieve Serial Clock
CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RSMRST, ACTIVE);
// Stall until GBLCTL reads back to ensure it was latched by the logic
while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RSMRST)!=CSL_MCASP_GBLCTL_RSMRST_ACTIVE);
}
if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XFRST)!=CSL_MCASP_GBLCTL_XFRST_ACTIVE){
//Start Recieve Serial Clock
CSL_FINST(mcaspRegs->XGBLCTL, MCASP_XGBLCTL_XFRST, ACTIVE);
//Stall until GBLCTL reads back to ensure it was latched by the logic
while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_XFRST)!=CSL_MCASP_GBLCTL_XFRST_ACTIVE);
}
if(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RFRST)!=CSL_MCASP_GBLCTL_RFRST_ACTIVE){
//Start Recieve Serial Clock
CSL_FINST(mcaspRegs->RGBLCTL, MCASP_RGBLCTL_RFRST, ACTIVE);
//Stall until GBLCTL reads back to ensure it was latched by the logic
while(CSL_FEXT(mcaspRegs->GBLCTL, MCASP_GBLCTL_RFRST)!=CSL_MCASP_GBLCTL_RFRST_ACTIVE);
}
return;
}
I have run the applications with xds100v2 probe and everything seems to be ok except the fact that I don't receive the data on AXR1[1]...
Something else is strange XSTAT and RSTAT are not correctly cleared during the sequence (as if it has no effect to write in) and the RCLOCKFAIL bit status remains set...
Is my procedure correct? Is it possible to echo I2s input data on output with clock signals coming from the codec ( in most of the case codec is considered as a slave device and it is OMAP which provide the clock...)
don't hesitate to ask for any details or clarifications
Thanks in advance
regards
vincent