Hello,
I observed some strange behavior while working with Starterware on BeagleBone regarding the Analog Inputs.
First of all, the SW-context:
Currently i´m programming some object oriented classes (Arduino Style) based on Starterware-Examples. In my Application i (can) use in parallel:
-Ethernet (TCP/IP) @ 100 Mbit (Thanks a lot to Tim49804 for his "interrupt workaround", in my stess-test i could transfer over 30 GB data @ 8 MB/s) with lwip 1.4.0
-UART0 @115200
-2x SPI @24 MHz
-All GPIOs (reconfigurable @runtime)
-(AN0 to AN7 , with limitations)
Additional:
-Starterware Version 02.00.00.07; Code Composer Studio 5.2.1.00018;
-D and I-Cache Enabled; Clock @ 720 MHz;
My Problems with "tsc_adc" @ Starterware API:
1. StepConfigure
I observed Measurements from wrong Channels. For Singleshot-Measurements of Analog 0 to Analog 6 I predefined the steps:
| //Define Measurements for all accesible analog Inputs, select needed "step" later. Single Measurements to Fifo0 StepConfigure(1, TSCADC_FIFO_0, TSCADC_POSITIVE_INP_CHANNEL1+1); // Configure step 1 for channel 1(AIN0) StepConfigure(2, TSCADC_FIFO_0, TSCADC_POSITIVE_INP_CHANNEL2+1); //(AIN1) StepConfigure(3, TSCADC_FIFO_0, TSCADC_POSITIVE_INP_CHANNEL3+1); //(AIN2) ... StepConfigure(7, TSCADC_FIFO_0, TSCADC_POSITIVE_INP_CHANNEL7+1); //(AIN6) |
Step Configure expands to:
| void BBgpio::StepConfigure(unsigned int stepSel, unsigned int fifo, unsigned int positiveInpChannel) { /* Configure ADC to Single ended operation mode */ TSCADCTSStepOperationModeControl(SOC_ADC_TSC_0_REGS, TSCADC_SINGLE_ENDED_OPER_MODE, stepSel); TSCADCTSStepConfig(SOC_ADC_TSC_0_REGS, stepSel, TSCADC_NEGATIVE_REF_VSSA, positiveInpChannel, TSCADC_NEGATIVE_INP_ADCREFM, TSCADC_POSITIVE_REF_VDDA); TSCADCTSStepFIFOSelConfig(SOC_ADC_TSC_0_REGS, stepSel, fifo); /* select fifo 0 or 1*/ TSCADCTSStepModeConfig(SOC_ADC_TSC_0_REGS, stepSel, TSCADC_ONE_SHOT_SOFTWARE_ENABLED); /* Configure ADC to one shot mode */ } |
Without the workaround "+1" the constant TSCADC_POSITIVE_INP_CHANNEL1 is defined (0), TSCADC_POSITIVE_INP_CHANNEL2 is defined (1) and so on.
Activation of step 1 and 2 (without "+1") both resulted in Measurements of AIN0, Step 3 up to Step 6 resulted in Measurements of AIN1 to AIN5. At AIN6, no measurement was possible.
After incrementing all constants (defined at "tsc_adc.h") with +1, the channel and values of AIN0 to AIN6 are correct.
Qestions:
Am I missing something?
Are the Analog Inputs not mapped correctly at Beaglebone? (schematic seems ok)
Any suggestions?
Reading the ID with (without "+1") TSCADCFIFOChannelIDRead (...) resulted in 0 to 6, what seems correct !?
Which leads to the second problem:
2. Fifo-read:
After sampling in Oneshot-mode, reading the resuts witch TSCADCFIFOADCDataRead (...) works fine.
But reading the ADC-Channel ID with TSCADCFIFOChannelIDRead(...) (if option is activated) for the next single sample and then getting the sample with TSCADCFIFOADCDataRead (...) results in 0.
Question:Is it possible that reading the Channel ID shifts the FIFO and the corresponding data is lost?
If yes, i will directly access FIFO0DATA Register and split ADCCHNLID and ADCDATA manually with a singel read.
3. Interrupt-Skipping
I trigger single Measurements for my higher API. Therefor i call following (trimmed) method:
|
int BBgpio::analogReadExt(unsigned int BBgpio){ //Enable and config corresponding to Analog Pin, activate steps adc_read=false; TSCADCEventInterruptEnable(SOC_ADC_TSC_0_REGS, TSCADC_END_OF_SEQUENCE_INT); // End of sequence interrupt is enable */ //Some error-Handling .... return analog_measurement; |
Problem: Activating TSC_ADC_SS module sometimes doesn´t result in an interrupt (probability 0.048%). Therefore waiting for the Flag could result in a Deadlock.
The code in Yellow generates a Timeout without interrupts or using Watchdogs(because I can not guarantee the availability of these resources) after approximately 7us.
The ADC-ISR:
| static void ADCIsr() { volatile unsigned int status; status = TSCADCIntStatus(SOC_ADC_TSC_0_REGS); TSCADCIntStatusClear(SOC_ADC_TSC_0_REGS, status); if(status & TSCADC_END_OF_SEQUENCE_INT) { adc_read=true; } adc_isr=true; } |
Questions:
What are the possible reasons, such an ADC-FSM interrupt can not occure?
Is there a possibility the Sequencer FSM doesn´t start sometimes (besides it is already running)?
Sorry for the long post. In exchange here are some performance results i´ve optained with ADC-Measurement so far:
Sampling duration: 21 minutes
Sampling count: 78.750 million at 62500 Samples/s
Sampling method: sequenze of single (each channel measurements starts sequenzer FSM) singleshots for AN0 to AN6
identified wrong measurements: 0.048% because of timeout
Thank you for your attention. I hope someone can give me hints regarding my questions.