DSI Configuration

Hi GSR,

Please refer to the following section on DSI namely "10.3.4.2 DSI Clock Configuration" under Display Subsystem in the OMAP4430 TRM in regards to DSI HS Command Mode configurations.

I will get back to you on the other queries soon.

Thanks & Best Regards,

Venkat

Hi Venkat,

Thank You for the reply and for your time.

I will get back here if we have any more questions.

Regards,

GSR

Venkat ,

Thanks for the clarification  ,  in continuation  to GSRs Question  ..

we are using the OMAP DISPC in video mode , These bits are set in the DISPC  ( DSI_CTRL_VP_VSYNC_START , DSI_CTRL_VP_VSYNC_END , 

DSI_CTRL_VP_HSYNC_START DSI_CTRL_VP_HSYNC_END)   and (/DSI_VC_CTRL_DCS_CMD_ENABLE ,  DSI_VC_CTRL_MODE)

1) will this condition enable the vsync and hsync from the dispc to the DSI .

2) Is there a way to verify if the DSI has received the Hsync and Vsync and has generated the sync packets to the client.

3)  Aafter the DDR_CLK_ALWAYS_ON is set we do not see clock on the DSI lanes immediately  , however , after a data transfer is initiated  we are able to see the clock continuously.

4) DSI_VC_CTRL_DCS_CMD_ENABLE  , is this bit need to be set in the video mode.

can you advise  

-Regards

SK

Hi Satish,

1) will this condition enable the vsync and hsync from the dispc to the DSI .

Ans.Yes, I think so. But as per my understanding, once you ensure that in DSI video mode, if the VSA bit field in DSI_VM_TIMING2 is set to 0x1 (other than 0x0), the vertical synchronization is enabled automatically. That is, when ever the VSYNC is received from the DISPC, VS is appended automatically in the DSI input.

3)  After the DDR_CLK_ALWAYS_ON is set we do not see clock on the DSI lanes immediately  , however , after a data transfer is initiated  we are able to see the clock continuously.

Ans. As I mentioned earlier, you need to send a NULL packet first to get the clock started. Only then the clock starts and continues since the  DDR_CLK_ALWAYS_ON is set.

Let me get back to you on other queries after some more investigation.

Thanks & Best Regards,

Venkat

Venkat ,

let me know if we can sync up over a call and understand more details about the use case scenario in our design.

-Regards

Satish

Hi Satish,

Coming back to your other queries.

2) Is there a way to verify if the DSI has received the Hsync and Vsync and has generated the sync packets to the client.

Answer: As long as DSI_VM_TIMING2 is set to other than 0, you are guaranteed to get sync packets generated to the client.

4) DSI_VC_CTRL_DCS_CMD_ENABLE  , is this bit need to be set in the video mode.

Answer: This is used for command mode only as per the description in the TRM. No need to set it for video mode.

Thanks & Best Regards,

Venkat

Thanks Venkat  ,

In our setup we are configuring the OMAP to video mode and the vsync and hsync are generated by the DISPC , the DSI is expected to generate Vsynv / hsync  short

packet which we are not seeing . how do we verify this?.

Also the DSI_VM_TIMING2 is non zero (set to 0x1) in our case .

-Regards

Satish

Venkat ,

we observe a  RESYNCHRONIZATION_IRQ  in the video mode  which indicates a timing  mismatch between DISPC and DSI , I am suspecting this may be causing the hsync and vsync  packets to be not generated . can you comment on this .

-Regards

Satish

Hi Satish,

Your understanding is correct. The timing mismatch between DISPC and DSI can lead to this RESYNCHRONIZATION_IRQ. To debug this, we need to know the following data points.

1. DISPC and DSI register dump

2. DISPC and DSI timing structures with their values

Also, it would be helpful if you can share the panel spec.

Could you also confirm if your panel supports only 1.01 MIPI standard or does it support 1.00 MIPI standard?

Thanks & Best Regards,

Venkat

Venkat , 

The OMAP is not driving the panel directly  , instead it  is driving a bridge (1.01 compliant ) .   we are verifying the DISPC and DSI registers and timing. shall post once we have the data.

-Thanks

Satish

Venkat, 

The  SYNCLOST1_IRQ  and the  VSYNC1_IRQ set in the  in the DISPC_IRQSTATUS  register.  Does this indicate  that the Vsync is not generated by the DISPC , I have attached the register dump for your reference.  

 6758.DISPC_GATED_Reg_Dump.txt

-Thanks

Satish

Hi Satish,

As per the TRM spec for OMAP4460, it can be seen that the above bit set implies that there is an issue with short blanking periods as described below.

SYNCLOST1_IRQ set implies:

Synchronization Lost on the primary LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least W1toClr
one pipelines associated with the primary LCD output.

VSYNC1_IRQ set implies:

Vertical Synchronization for the primary LCD.

I guess we need to ensure that the timings for the DISPC and DSI are programmed in accordance with the LVDS chip timings.

Could you please share the LVDS chip spec summarizing the timings information so that we can look into the reconfiguration of DISPC and DSI timings?

Also, share the current DISPC and DSI panel timing configurations.

Thanks & Best Regards,

Venkat

Venkat, 

The DISPC and  the DSI are configured for the Panel of  800x600 resolution with  hsw - 31  , hfp - 88  , hbp - 56  ,  vsw - 4 ,  vfp -13 , vbp -21.

 I am checking if  I can share the spec sheet due to  confidentiality , will share once I get an approval through your email id.

-Regards

Satish