Hi All,
In our application, FPGA generates BT1120 video timing, and outputs to VPIF, In normal condition, VPIF can work correctly. We configure VPIF as follow:
w=1600, h=1210, eav2sav=128, sav2eav=1934, l1=1, l3=3, l5=1213, vsize=1213.
But when externel event occurs, FPGA must discard current frame, and output a new one, in this condition, the discarded frame is not completed, But FPGA must asserts VPIF it is a completed frame, FPGA does the following things:
If frame is interrpted at N line, the rest lines is generated by FPGA, for each line: eav2sav=128, and sav2eav=24, Total line number is 1213 - N lines.
In most case VPIF can work well, but sometimes VPIF will lost the new frame. If snap 3 frames one time, only 2, 3 frame is received, and the first one is lost.
VPIF technical document don't refer to this application, We want to know, Our setting is satisfying VPIF timing, if not, How to do?
Thanks,
Richard You