I am reading spruh82a and having trouble understanding the relationship between EDMA3, EMIFA and the mapping of DMA requests from GPIO inputs.
I am using the MityARM-1808F board from Critical Link, which has a Xilinx Spartan 6 interfaced through EMIFA. I have address-mapped registers in the Spartan 6 which are working fine through EMIFA. All our code isbased on StarterWare.
The Spartan 6 is also connected to most of the GPIO. I want to use 4 lines on GP8 to generate interupts, and 4 lines of GP8 to generate 4 individual DMA requests.
I think I understand the interrupts. There will be one GP8 interrupt = Event 50 GPIO_B8INT GPIO Bank 8 Interrupt. The Interrupt Service Routine ISR would check INTSTAT8, take the appropriate action(s) and then clear the appropriate bit(s) of INTSTAT8. Is this correct?
For the EDMA, I don't see how the different lines of GP8 can be mapped to different DMA requests.
The section "17.2.4.1.1 Event-Triggered Transfer Request" says: "For the synchronization events associated with each of the programmable DMA channels, see your device-specific data manual to determine the event to channel mapping."
Is there more documentation about this?
Is there a better way to achieve the desired result?
